公开(公告)号：US20170250192A1

公开(公告)日：2017-08-31

申请号：US15489695

申请日：2017-04-17

申请人： Cypress Semiconductor Corporation

发明人： Ching-Huang LU ,  Simon S. Chan ,  Hidehiko Shiraiwa ,  Lei Xue

IPC分类号： H01L27/11568 ,  H01L29/51 ,  H01L29/792 ,  H01L29/66 ,  H01L21/265 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L29/423

摘要： An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

公开(公告)号：US09666591B2

公开(公告)日：2017-05-30

申请号：US15006288

申请日：2016-01-26

申请人： Cypress Semiconductor Corporation

发明人： Ching-Huang Lu ,  Simon Siu-Sing Chan ,  Hidehiko Shiraiwa ,  Lei Xue

IPC分类号： H01L29/02 ,  H01L27/11568 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51 ,  H01L29/423

CPC分类号： H01L27/11568 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/32053 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

公开(公告)号：US20160211271A1

公开(公告)日：2016-07-21

申请号：US15006288

申请日：2016-01-26

申请人： Cypress Semiconductor Corporation

发明人： Ching-Huang LU ,  Simon Siu-Sing CHAN ,  Hidehiko Shiraiwa ,  Lei Xue

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L23/532 ,  H01L29/51 ,  H01L23/528

CPC分类号： H01L27/11568 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/32053 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

公开(公告)号：US10692877B2

公开(公告)日：2020-06-23

申请号：US15489695

申请日：2017-04-17

申请人： Cypress Semiconductor Corporation

发明人： Ching-Huang Lu ,  Simon S. Chan ,  Hidehiko Shiraiwa ,  Lei Xue

IPC分类号： H01L21/26 ,  H01L27/11568 ,  H01L21/28 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L29/792 ,  H01L21/02 ,  H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51

摘要： An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

公开(公告)号：US09431503B2

公开(公告)日：2016-08-30

申请号：US14149521

申请日：2014-01-07

申请人： Cypress Semiconductor Corporation

发明人： Chuan Lin ,  Hidehiko Shiraiwa ,  Bradley Marc Davis ,  Lei Xue ,  Simon S. Chan ,  Kenichi Ohtsuka ,  Angela T. Hui ,  Scott Allan Bell

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/115 ,  H01L21/28

CPC分类号： H01L29/4916 ,  H01L21/28044 ,  H01L21/823456 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/78

摘要： An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.

摘要翻译： 集成电路包括第一多晶硅区域，第一多晶硅区域包括第一多晶硅层，设置在第一多晶硅层上的第二多晶硅层，与第一多晶硅层相关联的第一多硅指状物，以及 与第二多晶硅层相关联的第二多硅指状物。 第一多硅指状物和第二多晶硅指状物相对于彼此以基本上正交的方式取向。 集成电路包括包括第一多晶硅层的第二多晶硅栅极区域。 第一多晶硅栅极区域和第二多晶硅栅极区域各自具有不同的多晶硅栅极结构。