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公开(公告)号：US20190198125A1
公开(公告)日：2019-06-27
申请号：US16208841
申请日：2018-12-04
发明人： James Pak , Shivananda Shetty , Yoram Betser , Amichai Givant , Jonas Neo , Pawan Singh , Stefano Amato , Cindy Sun , Amir Rochman
摘要： A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.
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公开(公告)号：US11081194B2
公开(公告)日：2021-08-03
申请号：US16867828
申请日：2020-05-06
发明人： Chun Chen , Kuo Tung Chang , Yoram Betser , Shivananda Shetty , Giovanni Mazzeo , Tio Wei Neo , Pawan Singh
IPC分类号： G11C16/34 , G11C16/04 , G11C16/30 , G11C16/10 , G11C7/04 , G11C16/24 , G11C16/16 , G11C16/26
摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
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公开(公告)号：US10685724B2
公开(公告)日：2020-06-16
申请号：US16268736
申请日：2019-02-06
发明人： Chun Chen , Kuo Tung Chang , Yoram Betser , Shivananda Shetty , Giovanni Mazzeo , Tio Wei Neo , Pawan Singh
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34 , G11C16/30 , G11C7/04 , G11C16/24 , G11C16/16 , G11C16/26
摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
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公开(公告)号：US20180190361A1
公开(公告)日：2018-07-05
申请号：US15877633
申请日：2018-01-23
发明人： Chun Chen , Kuo-Tung Chang , Yoram Betser , Shivananda Shetty , Giovanni Mazzeo , Tio Wei Neo , Pawan Singh
CPC分类号： G11C16/3427 , G11C7/04 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30
摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.
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公开(公告)号：US20190279729A1
公开(公告)日：2019-09-12
申请号：US16268736
申请日：2019-02-06
发明人： Chun Chen , Kuo Tung Chang , Yoram Betser , Shivananda Shetty , Giovanni Mazzeo , Tio Wei Neo , Pawan Singh
IPC分类号： G11C16/34 , G11C16/26 , G11C16/16 , G11C16/24 , G11C7/04 , G11C16/30 , G11C16/04 , G11C16/10
摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
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公开(公告)号：US10229745B2
公开(公告)日：2019-03-12
申请号：US15877633
申请日：2018-01-23
发明人： Chun Chen , Kuo-Tung Chang , Yoram Betser , Shivananda Shetty , Giovanni Mazzeo , Tio Wei Neo , Pawan Singh
IPC分类号： G11C16/10 , G11C16/34 , G11C16/30 , G11C16/04 , G11C7/04 , G11C16/24 , G11C16/16 , G11C16/26
摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory device, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the flash memory device.
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公开(公告)号：US20200303023A1
公开(公告)日：2020-09-24
申请号：US16867828
申请日：2020-05-06
发明人： Chun Chen , Kuo Tung Chang , Yoram Betser , Shivananda Shetty , Giovanni Mazzeo , Tio Wei Neo , Pawan Singh
IPC分类号： G11C16/34 , G11C16/30 , G11C16/04 , G11C16/10 , G11C7/04 , G11C16/24 , G11C16/16 , G11C16/26
摘要： Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
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公开(公告)号：US10679712B2
公开(公告)日：2020-06-09
申请号：US16208841
申请日：2018-12-04
发明人： James Pak , Shivananda Shetty , Yoram Betser , Amichai Givant , Jonas Neo , Pawan Singh , Stefano Amato , Cindy Sun , Amir Rochman
摘要： A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.
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公开(公告)号：US09881683B1
公开(公告)日：2018-01-30
申请号：US15496993
申请日：2017-04-25
发明人： Chun Chen , Kuo-Tung Chang , Yoram Betser , Shivananda Shetty , Giovanni Mazzeo , Tio Wei Neo , Pawan Singh
CPC分类号： G11C16/3427 , G11C7/04 , G11C16/0425 , G11C16/0433 , G11C16/0466 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30
摘要： Techniques for suppression of program disturb in memory devices are described herein. In an example embodiment, a memory device comprises a flash memory array coupled to a control circuit. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). The control circuit is configured to regulate both a first voltage, of a selected SG line, and a second voltage, of an unselected BL, independently of a power supply voltage of the flash memory array, and to adjust at least one of the first voltage and the second voltage based on a measure of an operating temperature of the memory device.
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