公开(公告)号：US20210134811A1

公开(公告)日：2021-05-06

申请号：US16953643

申请日：2020-11-20

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  James Pak ,  Unsoon Kim ,  Inkuk Kang ,  Sung-Taeg Kang ,  Kuo Tung Chang

IPC分类号： H01L27/1157 ,  H01L27/11573 ,  H01L29/423

摘要： Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.

公开(公告)号：US20210091198A1

公开(公告)日：2021-03-25

申请号：US17039603

申请日：2020-09-30

申请人： Cypress Semiconductor Corporation

发明人： Shenqing Fang ,  Chun Chen ,  Unsoon KIM ,  Mark T. Ramsbey ,  Kuo Tung Chang ,  Sameer S. HADDAD ,  James Pak

IPC分类号： H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L29/49 ,  H01L29/788 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11568 ,  H01L27/11573 ,  H01L49/02

摘要： A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

公开(公告)号：US20190074286A1

公开(公告)日：2019-03-07

申请号：US16056183

申请日：2018-08-06

申请人： Cypress Semiconductor Corporation

发明人： Pawan Kishore Singh ,  Shivananda Shetty ,  James Pak

IPC分类号： H01L27/11568 ,  H01L21/28 ,  H01L29/06

摘要： An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.

公开(公告)号：US20180366551A1

公开(公告)日：2018-12-20

申请号：US16009543

申请日：2018-06-15

申请人： Cypress Semiconductor Corporation

发明人： Shenqing Fang ,  Chun Chen ,  Unsoon KIM ,  Mark Ramsbey ,  Kuo Tung Chang ,  Sameer HADDAD ,  James Pak

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L49/02 ,  H01L29/792 ,  H01L29/51 ,  H01L29/49 ,  H01L29/788 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/11568

CPC分类号： H01L29/42344 ,  H01L21/0214 ,  H01L21/0217 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

摘要： A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

公开(公告)号：US10068912B1

公开(公告)日：2018-09-04

申请号：US15614271

申请日：2017-06-05

申请人： Cypress Semiconductor Corporation

发明人： Pawan Kishore Singh ,  Shivananda Shetty ,  James Pak

IPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L29/06

摘要： A memory apparatus that has at least two non-volatile memory (NVM) cells disposed side by side overlying a substrate and an isolation structure disposed between the first and second NVM cells in the substrate. The first and second NVM cells share a common charge trapping layer that includes a continuous structure, and the portion of the common charge trapping layer that is disposed directly above the isolation structure includes a higher oxygen and/or nitrogen concentration than the portions of the common charge trapping layer that are disposed within the first and second NVM cells.

公开(公告)号：US20160293720A1

公开(公告)日：2016-10-06

申请号：US15181138

申请日：2016-06-13

申请人： Cypress Semiconductor Corporation

发明人： Shenqing Fang ,  Chun Chen ,  Unsoon Kim ,  Mark Ramsbey ,  Kuo Tung CHANG ,  Sameer HADDAD ,  James Pak

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L29/42344 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.

摘要翻译： 半导体器件包括：衬底，包括源极区和漏极区;形成在衬底上的位存储元件;存储器栅极结构;形成在衬底上的第一绝缘层;形成在衬底上的第二绝缘层;以及选择器 栅极结构形成在第一绝缘层上。 第二绝缘层形成在存储器栅极结构和选择栅极结构之间，以及存储栅极结构和选择栅极结构之间。

公开(公告)号：US11342429B2

公开(公告)日：2022-05-24

申请号：US17039603

申请日：2020-09-30

申请人： Cypress Semiconductor Corporation

发明人： Shenqing Fang ,  Chun Chen ,  Unsoon Kim ,  Mark T. Ramsbey ,  Kuo Tung Chang ,  Sameer S. Haddad ,  James Pak

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L29/49 ,  H01L29/788 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11568 ,  H01L27/11573 ,  H01L49/02

摘要： A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

公开(公告)号：US10403731B2

公开(公告)日：2019-09-03

申请号：US16009543

申请日：2018-06-15

申请人： Cypress Semiconductor Corporation

发明人： Shenqing Fang ,  Chun Chen ,  Unsoon Kim ,  Mark Ramsbey ,  Kuo Tung Chang ,  Sameer Haddad ,  James Pak

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L29/49 ,  H01L29/788 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11568 ,  H01L27/11573 ,  H01L49/02

摘要： A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

公开(公告)号：US20190198125A1

公开(公告)日：2019-06-27

申请号：US16208841

申请日：2018-12-04

申请人： Cypress Semiconductor Corporation

发明人： James Pak ,  Shivananda Shetty ,  Yoram Betser ,  Amichai Givant ,  Jonas Neo ,  Pawan Singh ,  Stefano Amato ,  Cindy Sun ,  Amir Rochman

IPC分类号： G11C16/34 ,  G11C16/28

摘要： A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.

公开(公告)号：US10242996B2

公开(公告)日：2019-03-26

申请号：US15848327

申请日：2017-12-20

申请人： Cypress Semiconductor Corporation

发明人： Chun Chen ,  James Pak ,  Unsoon Kim ,  Inkuk Kang ,  Sung-Taeg Kang ,  Kuo Tung Chang

IPC分类号： H01L27/11573 ,  H01L21/18 ,  H01L27/11546 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L27/11568 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L21/265 ,  H01L29/49

摘要： A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.