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    Copper interconnection structure incorporating a metal seed layer
    1.
    发明授权
    Copper interconnection structure incorporating a metal seed layer 有权
    包含金属种子层的铜互连结构

    公开(公告)号：US06399496B1

    公开(公告)日：2002-06-04

    申请号：US09714504

    申请日：2000-11-16

    申请人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

    发明人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.

    摘要翻译： 本发明公开了一种用于与电子设备进行电连接的互连结构，该电子设备包括基本上由铜形成的主体和不包含铜的铜合金或金属的籽晶层夹在铜导体本体和 用于提高互连结构的电迁移电阻，粘附性等表面性质的电子器件。 本发明还公开了用于形成互连结构的方法，该互连结构用于通过首先在电子器件上沉积铜合金或不含铜的其它金属的种子层，然后在其上形成铜导体，从而提供与电子器件的电连接 种子层紧密地结合到层上，使得互连结构的电迁移阻力，粘附性和其它表面性质得到改善。

    Copper interconnection structure incorporating a metal seed layer
    2.
    发明授权
    Copper interconnection structure incorporating a metal seed layer 失效
    包含金属种子层的铜互连结构

    公开(公告)号：US06181012B2

    公开(公告)日：2001-01-30

    申请号：US09067851

    申请日：1998-04-27

    申请人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

    发明人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

    IPC分类号： H01L23532

    CPC分类号： H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses, methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.

    摘要翻译： 本发明公开了一种用于与电子设备进行电连接的互连结构，该电子设备包括基本上由铜形成的主体和不包含铜的铜合金或金属的籽晶层夹在铜导体本体和 用于提高互连结构的电迁移电阻，粘附性等表面性质的电子器件。 本发明还公开了用于形成用于提供与电子设备的电连接的互连结构的方法，该方法是首先在电子设备上沉积不含铜的铜合金或其他金属种子层，然后在铜 种子层紧密地结合到层上，使得互连结构的电迁移阻力，粘附性和其它表面性质得到改善。

    Apparatus for electrochemical mechanical planarization
    3.
    发明授权
    Apparatus for electrochemical mechanical planarization 失效
    电化学机械平面化装置

    公开(公告)号：US5911619A

    公开(公告)日：1999-06-15

    申请号：US824747

    申请日：1997-03-26

    申请人： Cyprian Emeka Uzoh ,  James McKell Edwin Harper

    发明人： Cyprian Emeka Uzoh ,  James McKell Edwin Harper

    IPC分类号： H01L21/304 ,  B24B37/04 ,  B24B49/04 ,  B24B49/10 ,  B24B7/22

    CPC分类号： B24B37/26 ,  B24B37/046

    摘要： A method of planarizing a layer of a workpiece such as a semiconductor wafer includes rotating the layer against an electrolytic polishing slurry and flowing an electrical current through the slurry and through only one major side and/or minor sides of the layer, to remove portions of the layer. The one major side carries no microelectronic components which might be damaged by the current. At least a part of each step of rotating and of flowing occurs simultaneously. An apparatus for planarizing a layer includes a rotatable workpiece carrier, a rotatable platen arranged proximately to the carrier, a polishing pad mounted on the platen, and workpiece electrodes. The workpiece electrodes are movably attached to the carrier so as to engage electrically the minor sides of a layer when a workpiece is held on the carrier.

    摘要翻译： 平面化诸如半导体晶片的工件的层的方法包括使层抵抗电解抛光浆料旋转并使电流流过浆料并且仅通过层的一个主侧和/或次侧，以去除部分 层。 一个主要方面不存在可能被电流损坏的微电子元件。 旋转和流动的每个步骤的至少一部分同时发生。 用于平坦化层的装置包括可旋转工件载体，靠近载体布置的可旋转压板，安装在压板上的抛光垫和工件电极。 当工件被保持在载体上时，工件电极可移动地附接到载体以便电耦合层的次侧面。

    Method of electrochemical mechanical planarization
    6.
    发明授权
    Method of electrochemical mechanical planarization 失效
    电化学机械平面化方法

    公开(公告)号：US5807165A

    公开(公告)日：1998-09-15

    申请号：US827340

    申请日：1997-03-26

    申请人： Cyprian Emeka Uzoh ,  James McKell Edwin Harper

    发明人： Cyprian Emeka Uzoh ,  James McKell Edwin Harper

    IPC分类号： B24B37/04 ,  H01L21/306 ,  H01L21/3105 ,  B24B1/00

    CPC分类号： H01L21/31053 ,  B24B37/04

    摘要： A method of planarizing a layer of a workpiece such as a semiconductor wafer includes rotating the layer against an electrolytic polishing slurry and flowing an electrical current through the slurry and through only one major side and/or minor sides of the layer, to remove portions of the layer. The one major side carries no microelectronic components which might be damaged by the current. At least a part of each step of rotating and of flowing occurs simultaneously. An apparatus for planarizing a layer includes a rotatable workpiece carrier, a rotatable platen arranged proximately to the carrier, a polishing pad mounted on the platen, and workpiece electrodes. The workpiece electrodes are movably attached to the carrier so as to engage electrically the minor sides of a layer when a workpiece is held on the carrier.

    摘要翻译： 平面化诸如半导体晶片的工件的层的方法包括使层抵抗电解抛光浆料旋转并使电流流过浆料并且仅通过层的一个主侧和/或次侧移除部分 层。 一个主要方面不存在可能被电流损坏的微电子元件。 旋转和流动的每个步骤的至少一部分同时发生。 用于平坦化层的装置包括可旋转工件载体，靠近载体布置的可旋转压板，安装在压板上的抛光垫和工件电极。 当工件被保持在载体上时，工件电极可移动地附接到载体以便电耦合层的次侧面。

    Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
    7.
    发明授权
    Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 失效
    使用金属锗合金降低金属硅化物的接触电阻的方法和结构

    公开(公告)号：US06331486B1

    公开(公告)日：2001-12-18

    申请号：US09519897

    申请日：2000-03-06

    申请人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

    发明人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

    IPC分类号： H01L244

    CPC分类号： H01L21/28518

    摘要： A method of reducing contact resistance of metal silicides to a silicon-containing substrate is provided. The method includes first forming a metal germanium layer over a silicon-containing substrate. An optionally oxygen barrier layer may be formed over the metal germanium layer. Next, the structure containing the metal germanium layer is annealed at a temperature effective in converting at least a portion of the metal germanium layer into a substantially non-etchable metal silicide layer, while forming a Si-Ge interlayer between the substrate and the silicide layer. After annealing, the optional oxygen barrier layer and any remaining metal germanium layer is removed from the substrate.

    摘要翻译： 提供了一种降低金属硅化物与含硅衬底的接触电阻的方法。 该方法包括首先在含硅衬底上形成金属锗层。 可以在金属锗层上形成任选的氧阻挡层。 接下来，含有金属锗层的结构在有效地将金属锗层的至少一部分转化为基本上不可蚀刻的金属硅化物层的同时，在衬底和硅化物层之间形成Si-Ge中间层的温度下进行退火 。 在退火之后，从衬底去除可选的氧阻挡层和任何剩余的金属锗层。

    Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging
    8.
    发明授权
    Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging 有权
    使用金属硅合金自发对准形成硅化物接触的方法，用于有限的硅消耗和减少桥接

    公开(公告)号：US06323130B1

    公开(公告)日：2001-11-27

    申请号：US09515033

    申请日：2000-03-06

    申请人： Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Patricia Ann O'Neil ,  Yun Yu Wang

    发明人： Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Patricia Ann O'Neil ,  Yun Yu Wang

    IPC分类号： H01L2144

    CPC分类号： H01L29/665 ,  H01L21/28518

    摘要： A method of substantially reducing Si consumption and bridging during metal silicide contact formation comprising the steps of: (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to said metal silicon alloy or pure metal; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase. An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).

    摘要翻译： 一种在金属硅化物接触形成期间显着降低Si消耗和桥接的方法，包括以下步骤：（a）在含有电接触的电子器件的含硅衬底上形成金属硅合金层，所述合金层中的所述硅为 小于约30原子％，所述金属为Co，Ni或其混合物; （b）在约300℃至约500℃的温度下退火所述金属硅合金层，以便与所述金属硅合金或纯金属相比形成基本不可蚀刻的富金属硅化物层; （c）在非硅区域上有选择地去除任何未反应的金属硅合金; 和（d）在有效形成处于其最低电阻相的金属硅化物相的条件下退火所述富金属硅化物层。 可以在退火步骤（b）之前在金属硅合金层上形成任选的氧阻挡层。

    Multi-layer metal sandwich with taper and reduced etch bias and method for forming same
    9.
    发明授权
    Multi-layer metal sandwich with taper and reduced etch bias and method for forming same 失效
    具有锥形和减少的蚀刻偏压的多层金属夹层及其形成方法

    公开(公告)号：US5912506A

    公开(公告)日：1999-06-15

    申请号：US937349

    申请日：1997-09-20

    申请人： Evan G. Colgan ,  Peter M. Fryer ,  James McKell Edwin Harper ,  Kenneth P. Rodbell

    发明人： Evan G. Colgan ,  Peter M. Fryer ,  James McKell Edwin Harper ,  Kenneth P. Rodbell

    IPC分类号： G02F1/1362 ,  H01L23/498 ,  H01L23/538 ,  H01L23/48

    CPC分类号： H01L23/538 ,  H01L23/49866 ,  G02F2001/13629 ,  H01L2924/0002

    摘要： A multi-layer metal sandwich structure with taper and reduced etch bias formed on a substrate includes a first metal layer formed on the substrate and a second metal layer formed on the first metal layer. The width of the first metal layer is greater than the width of the second metal layer at the interface of the first metal layer and the second metal layer. The second metal layer has tapered side walls. The taper angle between each side wall and the intersection of the first and second metal layers is between 5.degree. and 90.degree.. The multi-layer metal sandwich may also include a third metal layer formed on the second metal layer.

    摘要翻译： 在衬底上形成具有锥形和减少的蚀刻偏压的多层金属夹层结构包括形成在衬底上的第一金属层和形成在第一金属层上的第二金属层。 第一金属层的宽度大于第一金属层和第二金属层的界面处的第二金属层的宽度。 第二金属层具有锥形侧壁。 每个侧壁与第一和第二金属层的交点之间的锥角在5°和90°之间。 多层金属夹层物还可以包括形成在第二金属层上的第三金属层。