公开(公告)号：US20210384406A1

公开(公告)日：2021-12-09

申请号：US17321819

申请日：2021-05-17

申请人： D-WAVE SYSTEMS INC.

发明人： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC分类号： H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/18 ,  H01L39/12

摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US11957065B2

公开(公告)日：2024-04-09

申请号：US17321819

申请日：2021-05-17

申请人： D-WAVE SYSTEMS INC.

发明人： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC分类号： H10N60/01 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10N60/85 ,  H10N69/00

CPC分类号： H10N60/0156 ,  H01L21/76891 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53285 ,  H10N60/85 ,  H10N69/00

摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US11038095B2

公开(公告)日：2021-06-15

申请号：US16481788

申请日：2018-01-31

申请人： D-WAVE SYSTEMS INC.

发明人： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC分类号： H01L27/18 ,  H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L39/12

摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.