公开(公告)号：US20160032462A1

公开(公告)日：2016-02-04

申请号：US14748399

申请日：2015-06-24

Applicant: DENSO CORPORATION

Inventor： Hitoshi YAMAGUCHI

IPC: C25B1/00 ,  C25B11/04 ,  C25B13/04 ,  C25B9/08 ,  H01G9/20 ,  C25B1/04

CPC classification number: C25B1/003 ,  C25B1/04 ,  C25B9/08 ,  C25B11/0405 ,  C25B11/0421 ,  C25B11/0447 ,  C25B13/04 ,  H01G9/2045 ,  Y02E60/364 ,  Y02E60/368

Abstract: A semiconductor photocatalyst includes first and second layers made of first and second materials, respectively. Band gaps of the first and second materials are equal to or smaller than 1.5 eV and 2.5 eV, respectively. A lower electric potential of a conduction band of the second material is disposed on a positive side from the first material. An upper electric potential of a valence band of the second material is disposed on a positive side from the first material and from an oxidation electric potential of water when the first and second layers are bonded to each other in the hetero junction manner. The lower electric potential of the conduction band of the first layer is disposed on a negative side from a reduction electric potential of hydrogen when the first and second layers are bonded to each other in the hetero junction manner.

Abstract translation: 半导体光催化剂包括分别由第一和第二材料制成的第一和第二层。 第一和第二材料的带隙分别等于或小于1.5eV和2.5eV。 第二材料的导带的较低电位设置在从第一材料的正侧。 当第一和第二层以异质连接方式彼此接合时，第二材料的价带的上电势被设置在从第一材料的正侧和水的氧化电位上。 当第一和第二层以异质连接方式彼此接合时，第一层的导带的较低的电位被设置在从氢的还原电位的负侧。

公开(公告)号：US20150100532A1

公开(公告)日：2015-04-09

申请号：US14456002

申请日：2014-08-11

Applicant: DENSO CORPORATION

Inventor： Hitoshi YAMAGUCHI

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where “1” is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where “0” is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses.

Abstract translation: 在神经元元件中的多输入栅电极的多个栅电极的一对一基础上提供多个突触确定电路。 对于与组信息相对应地重复输入“1”的第一图像区域，对应于第一图像区域的突触确定电路是兴奋性突触。 对于与组信息相对应地重复输入“0”的第二图像区域，对应于第二图像区域的突触确定电路是抑制性突触。

公开(公告)号：US20150041850A1

公开(公告)日：2015-02-12

申请号：US14513685

申请日：2014-10-14

Applicant: DENSO CORPORATION

Inventor： Hirotaka SAIKAKU ,  Tsuyoshi YAMAMOTO ,  Shoji MIZUNO ,  Masakiyo SUMITOMO ,  Tetsuo FUJII ,  Jun SAKAKIBARA ,  Hitoshi YAMAGUCHI ,  Yoshiyuki HATTORI ,  Rie TAGUCHI ,  Makoto KUWAHARA

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/7813 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7805 ,  H01L29/7819 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/861 ,  H01L2924/0002 ,  H02M7/003 ,  H01L2924/00

Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Abstract translation: 一种半导体器件包括：具有漂移层的开关元件; 基地区 在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。