公开(公告)号：US20190296149A1

公开(公告)日：2019-09-26

申请号：US16439023

申请日：2019-06-12

Applicant: DENSO CORPORATION

Inventor： Tsuyoshi YAMAMOTO ,  Kenta GODA ,  Shunsuke HARADA ,  Yoshiaki NAKAYAMA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/739

Abstract: In a semiconductor device, a trench is continuously connected to reach a main cell region and a sense cell region, and a shield electrode and a gate electrode layer are continuously connected to reach the main cell region and the sense cell region within the trench. The shield electrode extends to a side of the main cell region away from the sense cell region on one end side of the trench in a longitudinal direction to be electrically connected to an upper electrode. The gate electrode layer extends to a side of the main cell region away from the sense cell region on the other end side of the trench in the longitudinal direction to be electrically connected to a gate liner.

公开(公告)号：US20210184031A1

公开(公告)日：2021-06-17

申请号：US17117413

申请日：2020-12-10

Applicant: DENSO CORPORATION

Inventor： Tsuyoshi YAMAMOTO ,  Ryota SUZUKI ,  Yusuke YAMASHITA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66

Abstract: A SiC semiconductor device includes a main cell region and sense cell region being electrically isolated by an element isolation portion. The SiC semiconductor device includes a substrate, a first impurity region, a first current dispersion layer, first deep layers, a second current dispersion layer, a second deep layer, a base region, a trench gate structure, a second impurity region, first electrodes and a second electrode. The second impurity region, the first electrodes, and the second electrode are disposed at the main cell region and the sense cell region to form a vertical semiconductor element. The vertical semiconductor element allows a current flowing between the first electrode and the second electrode through a voltage applied to the gate electrode. The spacing interval between the deep layers at the element isolation portion is shorter than or equal to a spacing interval between the deep layers at the main cell region.

公开(公告)号：US20150041850A1

公开(公告)日：2015-02-12

申请号：US14513685

申请日：2014-10-14

Applicant: DENSO CORPORATION

Inventor： Hirotaka SAIKAKU ,  Tsuyoshi YAMAMOTO ,  Shoji MIZUNO ,  Masakiyo SUMITOMO ,  Tetsuo FUJII ,  Jun SAKAKIBARA ,  Hitoshi YAMAGUCHI ,  Yoshiyuki HATTORI ,  Rie TAGUCHI ,  Makoto KUWAHARA

IPC: H01L27/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/7813 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7805 ,  H01L29/7819 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/861 ,  H01L2924/0002 ,  H02M7/003 ,  H01L2924/00

Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Abstract translation: 一种半导体器件包括：具有漂移层的开关元件; 基地区 在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。