公开(公告)号：US12255228B2

公开(公告)日：2025-03-18

申请号：US17678661

申请日：2022-02-23

Applicant: FUJI ELECTRIC CO., LTD. ,  DENSO CORPORATION

Inventor： Masanobu Iwaya ,  Kensuke Hata

IPC: H01L29/15 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.

公开(公告)号：US09658121B2

公开(公告)日：2017-05-23

申请号：US14913067

申请日：2014-07-30

Applicant: DENSO CORPORATION

Inventor： Takashi Inoue ,  Kensuke Hata ,  Tetsuya Katoh ,  Kenichi Sakai ,  Mayumi Uno ,  Junichi Takeya

IPC: G01L1/22 ,  G01L1/18 ,  H01L51/05

CPC classification number: G01L1/2293 ,  G01L1/18 ,  H01L29/22 ,  H01L29/84 ,  H01L51/057

Abstract: A load sensor is constituted by a rib and a vertical transistor including an organic semiconductor film, and a load measurement can be executed based on a change of a gap between a drain electrode and a source electrode which is a channel length of the vertical transistor. Therefore, a change of a current Ids is in a linear relationship to a load applied to the load sensor.

公开(公告)号：US20250006795A1

公开(公告)日：2025-01-02

申请号：US18676897

申请日：2024-05-29

Applicant: FUJI ELECTRIC CO., LTD. ,  DENSO CORPORATION

Inventor： Naruhisa NAGATA ,  Yoshiuki Sugahara ,  Masanobu Iwaya ,  Tomohiro Mimura ,  Kensuke Hata

IPC: H01L29/16 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

Abstract: A method of manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide semiconductor substrate in which, on a front surface of a starting substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the starting substrate. Next, at the surface of the first semiconductor layer, a second semiconductor layer of a second conductivity type is formed. Next, at the surface of the second semiconductor layer, an ohmic electrode is formed. Next, at the surface of the ohmic electrode, a Ti film and a TiN film are sequentially deposited to form a barrier metal. Next, the barrier metal is subjected to a heat treatment to form an annealed barrier metal. The heat treatment is performed in a range of 550 degrees C. to 750 degrees C.

公开(公告)号：US11056584B2

公开(公告)日：2021-07-06

申请号：US16693598

申请日：2019-11-25

Applicant: DENSO CORPORATION

Inventor： Kensuke Hata ,  Shinichi Hoshi ,  Hideo Matsuki ,  Youngshin Eum ,  Shigeki Takahashi

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/423 ,  H01L29/80

Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.