公开(公告)号：US10714606B2

公开(公告)日：2020-07-14

申请号：US15753342

申请日：2016-09-05

Applicant: DENSO CORPORATION

Inventor： Youngshin Eum ,  Kazuhiro Oyama ,  Yasushi Higuchi ,  Yoshinori Tsuchiya ,  Shinichi Hoshi

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/812 ,  H01L29/205 ,  H01L29/872 ,  H01L29/40 ,  H01L29/20 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm−2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

公开(公告)号：US09818856B2

公开(公告)日：2017-11-14

申请号：US14347863

申请日：2012-10-17

Applicant: DENSO CORPORATION

Inventor： Shinichi Hoshi ,  Shoji Mizuno ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Kazuyoshi Tomita ,  Kenji Ito

IPC: H01L27/06 ,  H01L29/20 ,  H01L21/8234 ,  H01L29/16 ,  H01L21/388 ,  H01L29/15 ,  H01H3/20 ,  H01L27/07 ,  H01L29/74 ,  H01L29/778 ,  H01L29/66 ,  H01L21/762 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861

Abstract: A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.

公开(公告)号：US09728609B2

公开(公告)日：2017-08-08

申请号：US14389185

申请日：2012-11-01

Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  DENSO CORPORATION

Inventor： Tetsuo Narita ,  Kenji Ito ,  Kazuyoshi Tomita ,  Nobuyuki Otake ,  Shinichi Hoshi ,  Masaki Matsui

IPC: H01L29/15 ,  H01L29/20 ,  C30B29/40 ,  H01L21/02 ,  C30B25/08 ,  C30B25/18 ,  H01L29/04 ,  H01L33/00

CPC classification number: H01L29/2003 ,  C30B25/08 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/0254 ,  H01L29/045 ,  H01L33/007

Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.

公开(公告)号：US10381469B2

公开(公告)日：2019-08-13

申请号：US15101156

申请日：2014-08-28

Applicant: DENSO CORPORATION

Inventor： Yoshinori Tsuchiya ,  Shinichi Hoshi ,  Kazuyoshi Tomita ,  Kenji Itoh ,  Masahito Kodama ,  Tsutomu Uesugi

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/417 ,  H01L29/04 ,  H01L29/66 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.

公开(公告)号：US10121663B2

公开(公告)日：2018-11-06

申请号：US15320799

申请日：2015-03-26

Applicant: DENSO CORPORATION

Inventor： Yoshinori Tsuchiya ,  Hiroyuki Tarumi ,  Shinichi Hoshi ,  Masaki Matsui ,  Kenji Itoh ,  Tetsuo Narita ,  Tetsu Kachi

IPC: H01L21/223 ,  H01L21/20 ,  H01L29/786 ,  H01L29/04 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L21/28 ,  H01L29/417 ,  H01L29/51

Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm−3.

公开(公告)号：US20140231874A1

公开(公告)日：2014-08-21

申请号：US14347863

申请日：2012-10-17

Applicant: DENSO CORPORATION

Inventor： Shinichi Hoshi ,  Shoji Mizuno ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Kazuyoshi Tomita ,  Kenji Ito

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861

Abstract: A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.

Abstract translation: 半导体器件包括HEMT和二极管。 HEMT包括：在GaN层上具有GaN层作为产生二维电子气体的沟道层和AlGaN层作为阻挡层的衬底; 在与AlGaN层接触的AlGaN层上的源电极; 位于AlGaN层上的漏电极，与源极电极隔开，并与欧姆接触AlGaN层; 在源电极和漏电极之间的AlGaN层上的层间绝缘膜; 以及层间绝缘膜上的栅电极。 衬底包括在GaN层中产生二维电子气的有源层区域。 二极管包括电连接到栅电极的阳极和与漏电极电连接的阴极。

公开(公告)号：US12188151B2

公开(公告)日：2025-01-07

申请号：US18069366

申请日：2022-12-21

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Hiroaki Fujibayashi ,  Masatake Nagaya ,  Junji Ohara ,  Shinichi Hoshi ,  Takashi Kanemura

IPC: C30B29/36 ,  C30B25/20 ,  H01L21/683 ,  H01L21/78 ,  H01L29/16

Abstract: A silicon carbide wafer includes a base wafer that is made of silicon carbide and doped with an n-type impurity, and an epitaxial layer that is arranged on a main surface of the base wafer, made of silicon carbide and doped with an n-type impurity. The base wafer has a thickness t1 and an average impurity concentration n1, and the epitaxial layer has a thickness t2 and an average impurity concentration n2. The base wafer and the epitaxial layer are configured so as to satisfy a mathematical formula 1: −0.0178

公开(公告)号：US20220352027A1

公开(公告)日：2022-11-03

申请号：US17708490

申请日：2022-03-30

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation ,  National University Corporation Tokai National Higher Education and Research System ,  HAMAMATSU PHOTONICS K.K.

Inventor： Shinichi Hoshi ,  Masatake Nagaya ,  Chiaki Sasaoka ,  Daisuke Kawaguchi ,  Keisuke Hara

IPC: H01L21/78 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02

Abstract: A semiconductor chip includes a chip constituent substrate having a first surface and a second surface, and including a layer containing gallium nitride. The chip constituent substrate is provided with a semiconductor element, and components constituting the semiconductor element are located more in an area adjacent to the first surface than in an area adjacent to the second surface. The chip constituent substrate is formed with a through hole penetrating the chip constituent substrate from the first surface to the second surface. The through hole defines a first opening adjacent to the first surface and a second opening adjacent to the second surface, and the first opening is larger than the second opening.

公开(公告)号：US11056584B2

公开(公告)日：2021-07-06

申请号：US16693598

申请日：2019-11-25

Applicant: DENSO CORPORATION

Inventor： Kensuke Hata ,  Shinichi Hoshi ,  Hideo Matsuki ,  Youngshin Eum ,  Shigeki Takahashi

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/423 ,  H01L29/80

Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.

公开(公告)号：US10403745B2

公开(公告)日：2019-09-03

申请号：US15578403

申请日：2016-06-14

Applicant: DENSO CORPORATION

Inventor： Yasushi Higuchi ,  Shinichi Hoshi ,  Kazuhiro Oyama

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  H01L29/10

Abstract: A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.