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公开(公告)号:US11735654B2
公开(公告)日:2023-08-22
申请号:US17510913
申请日:2021-10-26
Applicant: DENSO CORPORATION
Inventor: Aiko Kaji , Yuichi Takeuchi , Shuhei Mitani , Ryota Suzuki , Yusuke Yamashita
CPC classification number: H01L29/1095 , H01L29/0684 , H01L29/086 , H01L29/1608 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L21/046
Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.
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公开(公告)号:US10720492B2
公开(公告)日:2020-07-21
申请号:US16304783
申请日:2017-06-29
Applicant: DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA
Inventor: Yuichi Takeuchi , Shuhei Mitani , Katsumi Suzuki , Yusuke Yamashita
Abstract: The width of the p type guard ring is set to match the interval between the adjacent p type guard rings, and the width of the p type guard ring is made larger as the interval between the p type guard rings becomes larger. The width of the frame portion is basically equal to the width of the p type deep layer so that the interval between the frame portions is equal to the interval between the p type deep layers. This makes it possible to reduce the difference in formation areas of the trenches per unit area in the cell portion, the connection portion and the guard ring portion. Therefore, when the p type layer is formed, the difference in the amount of the p type layer embedding into the trenches per unit area also decreases and the thickness of the p type layer is equalized.
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公开(公告)号:US10446649B2
公开(公告)日:2019-10-15
申请号:US14652483
申请日:2013-12-19
Applicant: DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA
Inventor: Tomoo Morino , Shoji Mizuno , Yuichi Takeuchi , Akitaka Soeno , Yukihiko Watanabe
IPC: H01L29/16 , H01L29/78 , H01L29/10 , H01L27/088 , H01L29/12 , H01L21/761 , H01L29/06
Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.
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公开(公告)号:US10374079B2
公开(公告)日:2019-08-06
申请号:US15505267
申请日:2015-09-08
Applicant: DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA
Inventor: Hirotaka Saikaku , Jun Sakakibara , Shoji Mizuno , Yuichi Takeuchi
Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.
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公开(公告)号:US09954073B2
公开(公告)日:2018-04-24
申请号:US15113484
申请日:2015-01-14
Applicant: DENSO CORPORATION
Inventor: Nozomu Akagi , Jun Sakakibara , Shoji Mizuno , Yuichi Takeuchi
IPC: H01L29/66 , H01L29/78 , H01L21/04 , H01L29/36 , H01L29/16 , H01L23/544 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423
CPC classification number: H01L29/66068 , H01L21/0465 , H01L21/0475 , H01L23/544 , H01L29/0865 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/36 , H01L29/41741 , H01L29/4236 , H01L29/66734 , H01L29/7813 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.
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公开(公告)号:US11879171B2
公开(公告)日:2024-01-23
申请号:US17364604
申请日:2021-06-30
Applicant: DENSO CORPORATION
Inventor: Hiroaki Fujibayashi , Yuichi Takeuchi
IPC: C23C16/455 , C23C16/32
CPC classification number: C23C16/45557 , C23C16/325
Abstract: A semiconductor manufacturing device includes: a thin film formation portion that includes a chamber; and a supply gas unit that introduces a supply gas into the chamber. The supply gas unit includes: multiple supply pipes; a raw material flow rate controller that is installed on each of the multiple supply pipes, and controls a flow rate; a collective pipe that is connected to the multiple supply pipes, and generates a mixed gas; multiple distribution pipes connected to a downstream side of the collective pipe; a pressure controller that is installed on one distribution pipe, and adjusts a mixed gas pressure; and a distribution flow rate controller that is installed on a distribution pipe different from the distribution pipe provided with the pressure controller, and controls a flow rate of the mixed gas.
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公开(公告)号:US11769801B2
公开(公告)日:2023-09-26
申请号:US17477168
申请日:2021-09-16
Applicant: DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA
Inventor: Yuichi Takeuchi , Ryota Suzuki , Tatsuji Nagaoka , Sachiko Aoi
CPC classification number: H01L29/1608 , H01L21/02529 , H01L29/06 , H01L29/0623 , H01L29/0696 , H01L29/12 , H01L29/4236 , H01L29/66068 , H01L29/78 , H01L29/7813
Abstract: In a guard ring section of a silicon carbide semiconductor device, an electric field relaxation layer for relaxing an electric field is formed in a surface layer portion of a drift layer, so that electric field is restricted from penetrating between guard rings. Thus, an electric field concentration is relaxed. Accordingly, a SiC semiconductor device having a required withstand voltage is obtained.
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公开(公告)号:US11637198B2
公开(公告)日:2023-04-25
申请号:US17511014
申请日:2021-10-26
Applicant: DENSO CORPORATION
Inventor: Yuichi Takeuchi , Yasuhiro Ebihara , Masahiro Sugimoto , Yusuke Yamashita
Abstract: A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.
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公开(公告)号:US11201216B2
公开(公告)日:2021-12-14
申请号:US16802754
申请日:2020-02-27
Applicant: DENSO CORPORATION
Inventor: Aiko Kaji , Yuichi Takeuchi , Shuhei Mitani , Ryota Suzuki , Yusuke Yamashita
Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.
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公开(公告)号:US10790201B2
公开(公告)日:2020-09-29
申请号:US16278314
申请日:2019-02-18
Applicant: DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA
Inventor: Akira Amano , Takayuki Satomura , Yuichi Takeuchi , Katsumi Suzuki , Sachiko Aoi
Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.
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