公开(公告)号：US06972224B2

公开(公告)日：2005-12-06

申请号：US10400896

申请日：2003-03-27

Applicant: David C. Gilmer ,  Srikanth B. Samavedam ,  Philip J. Tobin

Inventor： David C. Gilmer ,  Srikanth B. Samavedam ,  Philip J. Tobin

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

公开(公告)号：US06787421B2

公开(公告)日：2004-09-07

申请号：US10219522

申请日：2002-08-15

Applicant: David C. Gilmer ,  Christopher C. Hobbs ,  Hsing-Huang Tseng

Inventor： David C. Gilmer ,  Christopher C. Hobbs ,  Hsing-Huang Tseng

IPC: H01L218234

CPC classification number: H01L21/823462 ,  H01L21/31604 ,  H01L21/3162 ,  H01L28/56 ,  Y10S438/981

Abstract: A semiconductor device (10) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric (16) is formed in a region of the device for higher voltage requirements, e.g. an I/O region (24). A thinner second gate dielectric (20) is formed in a region of the device for lower voltage requirements, e.g. a core device region (22). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide (26) is deposited over both dielectrics, followed by deposition of a gate electrode material (28). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.

Abstract translation: 具有两个不同栅介质厚度的半导体器件（10）使用单个高k电介质层，优选金属氧化物形成。 在器件的区域中形成较厚的第一栅极电介质（16），用于更高电压要求，例如， I / O区域（24）。 在器件的一个区域中形成较薄的第二栅极电介质（20），用于降低电压要求，例如， 核心设备区域（22）。 第一和第二电介质优选为二氧化硅或氧氮化物。 金属氧化物（26）沉积在两个电介质上，随后沉积栅电极材料（28）。 通过在形成每个晶体管的栅极电介质堆叠中使用单个金属氧化物层以及高质量的二氧化硅或氧氮化物电介质层，可以避免与金属氧化物的选择性蚀刻相关的问题，这可能与在 金属氧化物和损坏或处理过的表面。

公开(公告)号：US07683439B2

公开(公告)日：2010-03-23

申请号：US11685027

申请日：2007-03-12

Applicant: Srikanth B. Samavedam ,  David C. Gilmer ,  Mark V. Raymond ,  James K. Schaeffer

Inventor： Srikanth B. Samavedam ,  David C. Gilmer ,  Mark V. Raymond ,  James K. Schaeffer

IPC: H01L27/088

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/4908 ,  H01L29/4958

Abstract: A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.

Abstract translation: 半导体器件结构形成在半导体衬底之上并且在半导体衬底上方具有栅极电介质，并且在栅极电介质上方具有栅极。 在与栅极电介质的界面处的栅极包含过渡金属，碳和正电性元素。 过渡金属由钽，钛，铪，锆，钼和钨组成。 正电荷元素包括由IIA族元素，IIIB族元素和镧系元素组成的组中的一种。

公开(公告)号：US20080001202A1

公开(公告)日：2008-01-03

申请号：US11427980

申请日：2006-06-30

Applicant: James K. Schaeffer ,  David C. Gilmer ,  Mark V. Raymond ,  Philip J. Tobin ,  Srikanth B. Samavedam

Inventor： James K. Schaeffer ,  David C. Gilmer ,  Mark V. Raymond ,  Philip J. Tobin ,  Srikanth B. Samavedam

IPC: H01L29/94

CPC classification number: H01L27/1203 ,  H01L21/28105 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.

Abstract translation: 半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。 第一层基本上是无氧的。 响应于随后的热处理，功函数被第二导电层调制到期望的功函数。 第二层是导电含氧金属。 具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。 金属的第三层沉积在第二层上。 多晶硅层沉积在第三层上。 第三层防止多晶硅层和含氧层一起反应。

公开(公告)号：US07015153B1

公开(公告)日：2006-03-21

申请号：US10969634

申请日：2004-10-20

Applicant: Dina H. Triyoso ,  Olubunmi O. Adetutu ,  David C. Gilmer ,  Darrell Roan ,  James K. Schaeffer ,  Philip J. Tobin ,  Hsing H. Tseng

Inventor： Dina H. Triyoso ,  Olubunmi O. Adetutu ,  David C. Gilmer ,  Darrell Roan ,  James K. Schaeffer ,  Philip J. Tobin ,  Hsing H. Tseng

IPC: H01L21/31

CPC classification number: C23C14/0057 ,  C23C16/30 ,  C23C16/45527 ,  H01L21/28229 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.

Abstract translation: 一种用于形成半导体器件的至少一部分的方法包括提供半导体衬底，使第一前体气体流过衬底以形成覆盖半导体衬底的第一含金属层，并且在完成所述第一前体气体流动步骤 使第一含氘吹扫气体流过第一含金属层，将氘掺入第一含金属层并且还吹扫第一前体气体。 该方法还可以包括使第二前体气体流过第一含金属层以与第一含金属层反应以形成含金属化合物的层，并将第二含氘的净化气体流过含金属化合物的层 层将氘并入含金属化合物的层中并且还吹扫第二前体气体。

公开(公告)号：US06573160B2

公开(公告)日：2003-06-03

申请号：US09578404

申请日：2000-05-26

Applicant: William J. Taylor, Jr. ,  Marius Orlowski ,  David C. Gilmer ,  Prasad V. Alluri ,  Christopher C. Hobbs ,  Michael J. Rendon ,  Iuval R. Clejan

Inventor： William J. Taylor, Jr. ,  Marius Orlowski ,  David C. Gilmer ,  Prasad V. Alluri ,  Christopher C. Hobbs ,  Michael J. Rendon ,  Iuval R. Clejan

IPC: H01L2120

CPC classification number: H01L21/02667 ,  H01L21/02381 ,  H01L21/2022 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/6659

Abstract: Techniques for forming gate dielectric layers (702) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions (604, 606) are formed prior to formation of structures included in the gate structure (804) of the semiconductor device, where the gate structures (804) are preferably formed using low temperature operations that allow the amorphous silicon regions (604, 606) to remain in an amorphous state. Source/drain regions (1004, 1006) are formed in the amorphous silicon regions (604, 606), and then the substrate is annealed to recrystallize the amorphous regions.

Abstract translation: 提出了用于形成覆盖非晶衬底材料的栅介质层（702）的技术。 此外，提出了允许在掺杂操作中使用非晶硅的低温处理操作的技术。 在形成包括在半导体器件的栅极结构（804）中的结构之前形成非晶硅区域（604,606），其中栅极结构（804）优选地使用允许非晶硅区域（ 604,606）保持在非晶状态。 源极/漏极区（1004,1006）形成在非晶硅区（604,606）中，然后将衬底退火以使非晶区重结晶。

公开(公告)号：US08178401B2

公开(公告)日：2012-05-15

申请号：US11530058

申请日：2006-09-08

Applicant: David C. Gilmer ,  Srikanth B. Samavedam ,  Philip J. Tobin

Inventor： David C. Gilmer ,  Srikanth B. Samavedam ,  Philip J. Tobin

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

Abstract translation: 一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。 诸如HfO 2的栅极电介质（34）沉积在半导体衬底上。 牺牲层（35）接着沉积在栅极电介质上。 牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是 受牺牲层保护。 第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。 图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。 第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

公开(公告)号：US20070284677A1

公开(公告)日：2007-12-13

申请号：US11796164

申请日：2007-04-26

Applicant: Weng Chang ,  Boq-Kang Hu ,  Jamie Schaeffer ,  David C. Gilmer ,  Phil Tobin

Inventor： Weng Chang ,  Boq-Kang Hu ,  Jamie Schaeffer ,  David C. Gilmer ,  Phil Tobin

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

Abstract: A metal-oxide-semiconductor (MOS) transistor having a gate electrode comprising a metal oxynitride and a method of forming the same are provided. The metal oxynitride preferably comprises molybdenum oxynitride and/or iridium oxynitride. The gate electrode may further comprise carbon and/or silicon. The gate electrode is preferably formed in a chamber containing nitrogen, oxygen and a carbon-containing gas. The gate electrode of the MOS transistor has a high work function and a low equivalent oxide thickness.

Abstract translation: 提供具有包含金属氮氧化物的栅电极的金属氧化物半导体（MOS）晶体管及其形成方法。 金属氮氧化物优选包含氮氧化钼和/或氮氧化铱。 栅极可以进一步包括碳和/或硅。 栅电极优选形成在含有氮，氧和含碳气体的室中。 MOS晶体管的栅电极具有高功函数和低当量氧化物厚度。

公开(公告)号：US06717226B2

公开(公告)日：2004-04-06

申请号：US10098706

申请日：2002-03-15

Applicant: Rama I. Hegde ,  Joe Mogab ,  Philip J. Tobin ,  Hsing H. Tseng ,  Chun-Li Liu ,  Leonard J. Borucki ,  Tushar P. Merchant ,  Christopher C. Hobbs ,  David C. Gilmer

Inventor： Rama I. Hegde ,  Joe Mogab ,  Philip J. Tobin ,  Hsing H. Tseng ,  Chun-Li Liu ,  Leonard J. Borucki ,  Tushar P. Merchant ,  Christopher C. Hobbs ,  David C. Gilmer

IPC: H01L2976

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Abstract translation: 晶体管器件具有至少两层的栅极电介质，其中一个是氧化铪，另一个是不同于氧化铪的金属氧化物。 氧化铪和金属氧化物也具有高介电常数。 金属氧化物提供与氧化铪的界面，其作为污染物渗透的屏障。 特别值得注意的是硼从多晶硅栅极渗透到氧化铪到半导体衬底。 氧化铪在其结晶结构中通常具有晶界，其提供硼原子的路径。 金属氧化物具有与氧化铪不同的结构，使得氧化铪中的硼的路径被金属氧化物阻挡。 因此，提供高介电常数，同时防止硼从栅电极渗透到基板。

公开(公告)号：US07868389B2

公开(公告)日：2011-01-11

申请号：US11928314

申请日：2007-10-30

Applicant: Olubunmi O. Adetutu ,  David C. Gilmer ,  Philip J. Tobin

Inventor： Olubunmi O. Adetutu ,  David C. Gilmer ,  Philip J. Tobin

IPC: H01L29/76

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Abstract translation: 可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。 在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。 在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。 在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数 与没有含硼物质的含金属栅电极相比。