公开(公告)号：US07494856B2

公开(公告)日：2009-02-24

申请号：US11393340

申请日：2006-03-30

申请人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/76254 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78684

摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

摘要翻译： 半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。 形成覆盖有源半导体层的栅电极。 蚀刻有源半导体层的源极/漏极区域以露出ESL。 源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。 形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。 优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。 可以使用加热至约75℃温度的NH 4 OH:H 2溶液进行湿式蚀刻来蚀刻源极/漏极区域。 ESL可以是具有第一百分比的锗的硅锗。 源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。

公开(公告)号：US07067868B2

公开(公告)日：2006-06-27

申请号：US10952676

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78687

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

公开(公告)号：US07018901B1

公开(公告)日：2006-03-28

申请号：US10954121

申请日：2004-09-29

申请人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

发明人： Voon-Yew Thean ,  Mariam G. Sadaka ,  Ted R. White ,  Alexander L. Barr ,  Venkat R. Kolagunta ,  Bich-Yen Nguyen ,  Victor H. Vartanian ,  Da Zhang

IPC分类号： H01L21/336

CPC分类号： H01L21/2254 ,  H01L29/665 ,  H01L29/66787 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78648

摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

摘要翻译： 半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。 例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。 热处理将应力源材料扩散到半导体层。 发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。 延伸植入物从应力源材料层的第一部分产生源和漏植入物。 应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。 因此，在应变通道中形成异质结。 在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

公开(公告)号：US07226820B2

公开(公告)日：2007-06-05

申请号：US11101354

申请日：2005-04-07

申请人： Da Zhang ,  Jing Liu ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted R. White

发明人： Da Zhang ,  Jing Liu ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted R. White

IPC分类号： H01L21/00

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

摘要翻译： 半导体制造工艺包括形成覆盖在半导体衬底（102）上的栅电介质（110）上的栅电极（120）。 第一间隔物（124）形成在栅电极（120）的侧壁上。 使用栅电极（120）和第一间隔物（124）作为掩模，在基板（102）中形成第一s / d沟槽（130）。 第一s / d沟槽（130）填充有第一s / d结构（132）。 第二间隔物（140）形成在邻近第一间隔物（124）的栅电极（120）侧壁上。 使用栅电极（120）和第二间隔物（140）作为掩模，在衬底（102）中形成第二s / d沟槽（150）。 第二s / d沟槽（150）填充有第二s / d结构（152）。 填充第一和第二s / d沟槽（130,150）优选地包括使用外延工艺来生长s / d结构。 s / d结构（132,152）可以是应力诱导结构，例如用于PMOS晶体管的硅锗和用于NMOS晶体管的硅碳。

公开(公告)号：US07538002B2

公开(公告)日：2009-05-26

申请号：US11361171

申请日：2006-02-24

申请人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

发明人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

摘要翻译： 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

公开(公告)号：US20080296620A1

公开(公告)日：2008-12-04

申请号：US12174357

申请日：2008-07-16

申请人： Da Zhang ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Bich-Yen Nguyen

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66507 ,  H01L29/66795 ,  H01L29/78684

摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

摘要翻译： 电子器件可以包括覆盖绝缘层的半导体鳍片。 电子器件还可以包括覆盖半导体鳍片的半导体层。 半导体层可以具有彼此间隔开的第一部分和第二部分。 在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。 电子器件还可以包括覆盖半导体层的金属 - 半导体层。 在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。 在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。 在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

公开(公告)号：US20060228863A1

公开(公告)日：2006-10-12

申请号：US11092291

申请日：2005-03-29

申请人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

发明人： Da Zhang ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Yasuhito Shiho ,  Veer Dhandapani

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

摘要翻译： 通过提供半导体衬底和具有侧壁的上覆控制电极来形成具有应变增强的半导体器件。 在控制电极的侧壁附近形成绝缘层。 注入半导体衬底和控制电极以形成第一和第二掺杂电流电极区域，第一和第二掺杂电流电极区域中的每一个的一部分被驱动以在第一和第二掺杂电流电极区域的沟道区域中的绝缘层和控制电极之下 半导体器件。 第一和第二掺杂电流电极区域除了在控制电极和绝缘层之下除去分别形成第一和第二沟槽的半导体衬底外。 在第一沟槽和第二沟槽内形成含有相对于半导体衬底的不同晶格常数的原位掺杂材料，用作半导体器件的第一和第二电流电极。

公开(公告)号：US20060228842A1

公开(公告)日：2006-10-12

申请号：US11101354

申请日：2005-04-07

申请人： Da Zhang ,  Jing Liu ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

发明人： Da Zhang ,  Jing Liu ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/338 ,  H01L21/20

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

摘要翻译： 半导体制造工艺包括形成覆盖在半导体衬底（102）上的栅电介质（110）上的栅电极（120）。 第一间隔物（124）形成在栅电极（120）的侧壁上。 使用栅电极（120）和第一间隔物（124）作为掩模，在基板（102）中形成第一s / d沟槽（130）。 第一s / d沟槽（130）填充有第一s / d结构（132）。 第二间隔物（140）形成在邻近第一间隔物（124）的栅电极（120）侧壁上。 使用栅电极（120）和第二间隔物（140）作为掩模，在衬底（102）中形成第二s / d沟槽（150）。 第二s / d沟槽（150）填充有第二s / d结构（152）。 填充第一和第二s / d沟槽（130,150）优选地包括使用外延工艺来生长s / d结构。 s / d结构（132,152）可以是应力诱导结构，例如用于PMOS晶体管的硅锗和用于NMOS晶体管的硅碳。

公开(公告)号：US07800141B2

公开(公告)日：2010-09-21

申请号：US12174357

申请日：2008-07-16

申请人： Da Zhang ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Bich-Yen Nguyen

IPC分类号： H01L29/06

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66507 ,  H01L29/66795 ,  H01L29/78684

摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

摘要翻译： 电子器件可以包括覆盖绝缘层的半导体鳍片。 电子器件还可以包括覆盖半导体鳍片的半导体层。 半导体层可以具有彼此间隔开的第一部分和第二部分。 在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。 电子器件还可以包括覆盖半导体层的金属 - 半导体层。 在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。 在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。 在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

公开(公告)号：US07446026B2

公开(公告)日：2008-11-04

申请号：US11349595

申请日：2006-02-08

申请人： Da Zhang ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Bich-Yen Nguyen

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/823814 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.

摘要翻译： 一种用于形成半导体器件的方法包括提供具有第一掺杂区域和第二掺杂区域的半导体衬底，在第一掺杂区域和第二掺杂区域上提供电介质，以及在电介质上至少形成第一栅极叠层 第一掺杂区域的一部分。 第一栅极堆叠包括电介质上的金属部分，金属部分上方的第一原位掺杂半导体部分以及原位掺杂半导体部分上的第一阻挡盖。 该方法还包括执行注入以形成与第一和第二栅极堆叠相邻的源极/漏极区域，其中第一阻挡盖具有足以基本上阻挡注入掺杂剂进入第一原位掺杂半导体部分的厚度。 源/漏嵌入式应力源也形成。