公开(公告)号：US08143680B2

公开(公告)日：2012-03-27

申请号：US12778912

申请日：2010-05-12

申请人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

发明人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC分类号： H01L29/66 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/66356

摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

摘要翻译： 门控二极管半导体器件或类似部件及其制造方法。 该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且与源极和漏极相邻。 源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。 这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。 如果两者都存在，则源极和漏极可以是对称的或非对称的。 这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

公开(公告)号：US07732877B2

公开(公告)日：2010-06-08

申请号：US11731963

申请日：2007-04-02

申请人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

发明人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/66356

摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

摘要翻译： 门控二极管半导体器件或类似部件及其制造方法。 该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且邻近源极和漏极。 源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。 这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。 如果两者都存在，则源极和漏极可以是对称的或非对称的。 这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

公开(公告)号：US20080237746A1

公开(公告)日：2008-10-02

申请号：US11731963

申请日：2007-04-02

申请人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

发明人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/66356

摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

摘要翻译： 门控二极管半导体器件或类似部件及其制造方法。 该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且与源极和漏极相邻。 源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。 这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。 如果两者都存在，则源极和漏极可以是对称的或非对称的。 这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

公开(公告)号：US06673683B1

公开(公告)日：2004-01-06

申请号：US10291029

申请日：2002-11-07

申请人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

发明人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

IPC分类号： H01L21336

CPC分类号： H01L29/66553 ,  H01L29/66545 ,  H01L29/6659

摘要： A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.

摘要翻译： 在半导体产品中形成场效应晶体管器件的方法当形成一对源极/漏极区域时首先使用图案化虚拟层作为离子注入掩模层，然后作为用于形成一对图案化牺牲层的心轴层， 限定对应于图案化虚拟层的线宽和位置的孔径。 然后在孔内自对准地形成一对牺牲间隔层和栅电极。 然后剥去一对图案化牺牲层和一对牺牲隔离层，并且使用栅电极作为用于离子注入的掩模，形成与半导体衬底内的一对源/漏区部分重叠的一对轻掺杂的延伸区。

公开(公告)号：US09595443B2

公开(公告)日：2017-03-14

申请号：US13277642

申请日：2011-10-20

申请人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

发明人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC分类号： H01L21/70 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层 其中富氮TiN层在隔离区域上连接到含氧TiN层。

公开(公告)号：US07342289B2

公开(公告)日：2008-03-11

申请号：US10637351

申请日：2003-08-08

申请人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

IPC分类号： H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

摘要翻译： 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

公开(公告)号：US06368928B1

公开(公告)日：2002-04-09

申请号：US09878455

申请日：2001-06-12

申请人： Howard Chih-Hao Wang ,  Su-Yu Lu ,  Mu-Chi Chiang ,  Yu-Sen Chu ,  Chao-Jie Tsai ,  Carlos H. Diaz

发明人： Howard Chih-Hao Wang ,  Su-Yu Lu ,  Mu-Chi Chiang ,  Yu-Sen Chu ,  Chao-Jie Tsai ,  Carlos H. Diaz

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L29/1083

摘要： A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region, with an initial indium profile, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, a low temperature anneal procedure is used to activate indium ions in the initial indium pocket region, and to create a final indium pocket region, featuring a final indium profile. The final indium profile remains unchanged after experiencing subsequent high temperature procedures, such as a post-heavily doped, source/drain anneal. The narrow channel length NMOS devices, fabricated using the low temperature anneal procedure described in this invention, resulted in a reduced Vt roll-off phenomena, when compared to counterpart, narrow channel length NMOS, formed without the benefit of the low temperature anneal procedure.

摘要翻译： 已经开发了形成注入口袋区域以减少窄沟道长度的信道效应（SCE）的方法，即NMOS器件。 在形成具有初始铟分布的初始铟袋区域之后，在用于容纳N型源极/漏极区域的P型半导体区域中，使用低温退火程序来激活初始铟中的铟离子 口袋区域，并创建最终的铟口袋区域，具有最终的铟型材。 在经历随后的高温程序（例如重掺杂的源极/漏极退火）之后，最终的铟分布保持不变。 使用本发明中描述的低温退火方法制造的窄沟道长度的NMOS器件，与对比的窄沟道长度NMOS相比，导致了减小的Vt滚降现象，而窄通道长度NMOS则不受低温退火工艺的影响。

公开(公告)号：US08669163B2

公开(公告)日：2014-03-11

申请号：US12898421

申请日：2010-10-05

申请人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

发明人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC分类号： H01L21/336

CPC分类号： H01L29/7391 ,  H01L21/26586

摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

公开(公告)号：US07834345B2

公开(公告)日：2010-11-16

申请号：US12205585

申请日：2008-09-05

申请人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

发明人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC分类号： H01L29/94

CPC分类号： H01L29/7391 ,  H01L21/26586

摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

公开(公告)号：US20100059737A1

公开(公告)日：2010-03-11

申请号：US12205585

申请日：2008-09-05

申请人： Krishna Kumar Bhuwalka ,  Chin-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

发明人： Krishna Kumar Bhuwalka ,  Chin-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC分类号： H01L29/15

CPC分类号： H01L29/7391 ,  H01L21/26586

摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。