Semiconductor memory device and method for operating the same
    1.
    发明授权
    Semiconductor memory device and method for operating the same 有权
    半导体存储器件及其操作方法

    公开(公告)号:US08253465B2

    公开(公告)日:2012-08-28

    申请号:US13186366

    申请日:2011-07-19

    IPC分类号: H03K3/00 H03K5/13 H03H11/16

    摘要: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

    摘要翻译: 半导体存储器件包括边缘检测器,被配置为接收两对互补时钟以检测时钟的边沿;比较器,被配置为比较边缘检测器的输出信号,以检测同一对的时钟是否具有180度的相位差;以及 检测不同对的时钟是否具有90度的相位差,控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器,被配置为校正时钟的相位 响应于控制信号。

    Duty detection circuit
    2.
    发明授权
    Duty detection circuit 有权
    占空比检测电路

    公开(公告)号:US07612593B2

    公开(公告)日:2009-11-03

    申请号:US12005923

    申请日:2007-12-28

    IPC分类号: H03K5/02

    摘要: Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation.

    摘要翻译: 具有占空比校正电路的半导体存储器件包括:时钟边缘检测器,被配置为响应于在初始测量操作中的公共时钟信号的转变定时产生第一和第二检测脉冲; 负载检测器,被配置为将所述第一和第二检测脉冲与输出比较结果信号进行比较; 以及代码计数器,被配置为基于在初始测量操作中从占空比检测器输出的比较信号来控制占空比检测器。

    FLIP-FLOP CIRCUIT AND DUTY RATIO CORRECTION CIRCUIT USING THE SAME
    3.
    发明申请
    FLIP-FLOP CIRCUIT AND DUTY RATIO CORRECTION CIRCUIT USING THE SAME 有权
    FLIP-FLOP电路和占空比校正电路

    公开(公告)号:US20090085624A1

    公开(公告)日:2009-04-02

    申请号:US12240166

    申请日:2008-09-29

    IPC分类号: H03K3/017 H03K3/356

    CPC分类号: H03K3/017 H03K3/356104

    摘要: A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal.

    摘要翻译: 触发器电路包括被配置为接收参考时钟信号和复位信号的第一单元和被配置为响应于参考时钟信号将输出节点改变到第一电平的第二单元,并将输出节点改变为第二电平 根据复位信号,响应于从第一单元输出的信号预先输出输出节点的电平。

    Duty cycle ratio correction circuit
    4.
    发明授权
    Duty cycle ratio correction circuit 有权
    占空比修正电路

    公开(公告)号:US08836397B2

    公开(公告)日:2014-09-16

    申请号:US12240166

    申请日:2008-09-29

    IPC分类号: H03K3/00 H03K3/017 H03K3/356

    CPC分类号: H03K3/017 H03K3/356104

    摘要: A duty ratio correction circuit includes a duty cycle ratio controlling unit configured to generate an internal clock signal having a duty cycle ratio defined according to a first reference clock signal and a reset signal and a reset signal generating unit configured to generate the reset signal in response to a second reference clock signal and the internal clock signal fed back thereto.

    摘要翻译: 占空比校正电路包括占空比比率控制单元,其被配置为产生具有根据第一参考时钟信号和复位信号定义的占空比的内部时钟信号,以及复位信号生成单元,被配置为响应于产生复位信号 到第二参考时钟信号和反馈到其的内部时钟信号。

    Semiconductor memory device and method for operating the same
    5.
    发明授权
    Semiconductor memory device and method for operating the same 有权
    半导体存储器件及其操作方法

    公开(公告)号:US08004336B2

    公开(公告)日:2011-08-23

    申请号:US12150912

    申请日:2008-05-01

    IPC分类号: H03H11/16 H03K5/13

    摘要: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

    摘要翻译: 半导体存储器件包括边缘检测器,被配置为接收两对互补时钟以检测时钟的边沿;比较器,被配置为比较边缘检测器的输出信号,以检测同一对的时钟是否具有180度的相位差;以及 检测不同对的时钟是否具有90度的相位差,控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器,被配置为校正时钟的相位 响应于控制信号。

    LOW PASS FILTER AND LOCK DETECTOR CIRCUIT
    6.
    发明申请
    LOW PASS FILTER AND LOCK DETECTOR CIRCUIT 有权
    低通滤波器和锁定检测电路

    公开(公告)号:US20090168944A1

    公开(公告)日:2009-07-02

    申请号:US12344552

    申请日:2008-12-28

    IPC分类号: H03D3/24

    摘要: A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.

    摘要翻译: 低通滤波器包括被配置为输出与输入脉冲宽度成比例的电压的驱动器单元,被配置为对驱动器单元的输出电压进行充电的充电/放电单元,被配置为比较充电/放电的输出电压 具有参考值的单元以输出方波信号;以及切换单元,被配置为基于带宽扩展信号将充电/放电单元切换到操作状态。

    APPARATUS AND METHOD FOR DETECTING DUTY RATIO OF SIGNALS IN SEMICONDUCTOR DEVICE CIRCUIT
    7.
    发明申请
    APPARATUS AND METHOD FOR DETECTING DUTY RATIO OF SIGNALS IN SEMICONDUCTOR DEVICE CIRCUIT 审中-公开
    用于检测半导体器件电路中信号占空比的装置和方法

    公开(公告)号:US20090128208A1

    公开(公告)日:2009-05-21

    申请号:US12263690

    申请日:2008-11-03

    IPC分类号: H03K3/017

    CPC分类号: H03K3/017

    摘要: Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals.

    摘要翻译: 用于检测半导体器件电路中的信号占空比的装置包括用于检测半导体器件中的信号的占空比的电路,包括比较单元,其比较差分输入的第一和第二输入时钟信号的占空比并产生第一输出信号, 第二输出信号,存储第一和第二输出信号并产生对应于第一和第二输出信号的检测信号的锁存单元,以及接收第一和第二输出信号的调整单元,并且发送第一和第二输出信号 基于第一和第二输出信号的电压电平差,向锁存单元输出第二输出信号。

    Counter with overflow prevention capability
    8.
    发明申请
    Counter with overflow prevention capability 失效
    具有防溢出功能的计数器

    公开(公告)号:US20090086881A1

    公开(公告)日:2009-04-02

    申请号:US12005933

    申请日:2007-12-28

    IPC分类号: G06M3/00

    CPC分类号: G06M3/12

    摘要: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

    摘要翻译: 具有防溢能力的计数器包括:计数单元,被配置为响应于输入信号对输出代码进行计数;以及溢出防止单元,被配置为当输出代码的当前值为最大值时,控制计数单元停止计数输出代码 值,但其前一值不是最大值。

    Low pass filter and lock detector circuit
    9.
    发明授权
    Low pass filter and lock detector circuit 有权
    低通滤波器和锁定检测电路

    公开(公告)号:US07876148B2

    公开(公告)日:2011-01-25

    申请号:US12344552

    申请日:2008-12-28

    IPC分类号: H03L7/093 H03L7/095

    摘要: A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.

    摘要翻译: 低通滤波器包括被配置为输出与输入脉冲宽度成比例的电压的驱动器单元,被配置为对驱动器单元的输出电压进行充电的充电/放电单元,被配置为比较充电/放电的输出电压 具有参考值的单元以输出方波信号;以及切换单元,被配置为基于带宽扩展信号将充电/放电单元切换到操作状态。

    Clock synchronization circuit and operation method thereof
    10.
    发明授权
    Clock synchronization circuit and operation method thereof 失效
    时钟同步电路及其操作方法

    公开(公告)号:US07855933B2

    公开(公告)日:2010-12-21

    申请号:US12165045

    申请日:2008-06-30

    IPC分类号: G11C8/00

    摘要: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

    摘要翻译: 一种具有时钟同步电路的半导体存储器件,其能够执行期望的相位/频率锁定操作,而没有抖动峰化现象和使用注入锁定的振荡控制电压信号的模式抖动。 该装置包括锁相环,其检测反馈时钟信号和参考时钟信号之间的相位/频率差,以产生对应于检测到的相位/频率差的振荡控制电压信号,并产生对应于 振荡控制电压信号。 注入锁定振荡单元响应于振荡控制电压信号建立自由运行频率,并产生与参考时钟信号同步的内部时钟信号。