公开(公告)号：US08357434B1

公开(公告)日：2013-01-22

申请号：US11304223

申请日：2005-12-13

申请人： Dae-han Choi ,  Jisoo Kim ,  Eric Hudson ,  Sangheon Lee ,  Conan Chiang ,  S. M. Reza Sadjadi

发明人： Dae-han Choi ,  Jisoo Kim ,  Eric Hudson ,  Sangheon Lee ,  Conan Chiang ,  S. M. Reza Sadjadi

IPC分类号： H05H1/24

CPC分类号： H01L21/0338 ,  H01J37/32082 ,  H01J37/32449 ,  H01J37/32724 ,  H01J37/32834

摘要： A method for depositing a conformal film on a substrate in a plasma processing chamber of a plasma processing system, the substrate being disposed on a chuck, the chuck being coupled to a cooling apparatus, is disclosed. The method includes flowing a first gas mixture into the plasma processing chamber at a first pressure, wherein the first gas mixture includes at least carbon, and wherein the first gas mixture has a condensation temperature. The method also includes cooling the chuck below the condensation temperature using the cooling apparatus thereby allowing at least some of the first gas mixture to condense on a surface of the substrate. The method further includes venting the first gas mixture from the processing chamber; flowing a second gas mixture into the plasma processing chamber, the second gas mixture being different in composition from the first gas mixture; and striking a plasma to form the conformal film.

摘要翻译： 公开了一种在等离子体处理系统的等离子体处理室中的基板上沉积保形膜的方法，该基板设置在卡盘上，该卡盘与冷却装置连接。 该方法包括在第一压力下将第一气体混合物流入等离子体处理室，其中第一气体混合物至少包括碳，并且其中第一气体混合物具有冷凝温度。 该方法还包括使用冷却装置将夹盘冷却至冷凝温度以下，从而允许至少一些第一气体混合物在基板的表面上冷凝。 该方法还包括从处理室排出第一气体混合物; 将第二气体混合物流入等离子体处理室，第二气体混合物的组成与第一气体混合物不同; 并冲击等离子体以形成保形膜。

公开(公告)号：US20060278339A1

公开(公告)日：2006-12-14

申请号：US11152016

申请日：2005-06-13

申请人： Jisoo Kim ,  Dae-han Choi ,  S.M. Sadjadi

发明人： Jisoo Kim ,  Dae-han Choi ,  S.M. Sadjadi

IPC分类号： C23F1/00

CPC分类号： H01J37/32091 ,  H01J37/32165 ,  H01J37/32568 ,  H01J37/32623

摘要： A plasma reactor comprises a chamber, a bottom electrode, a top electrode, a bottom grounded extension adjacent to and substantially encircling the bottom electrode. The top grounded extension adjacent to and substantially parallel to the top electrode. The top electrode is also grounded. The top grounded extension is capable of being independently raised or lowered to extend into a region above the bottom grounded extension.

摘要翻译： 等离子体反应器包括腔室，底部电极，顶部电极，与底部电极相邻并且基本上环绕底部电极的底部接地延伸部。 邻近并基本平行于顶部电极的顶部接地延伸部分。 顶部电极也接地。 顶部接地延伸部能够独立地升高或降低以延伸到底部接地延伸部上方的区域中。

公开(公告)号：US20130224944A1

公开(公告)日：2013-08-29

申请号：US13405414

申请日：2012-02-27

申请人： Puneet Khanna ,  Dae-han Choi ,  Katherina Babich ,  Catherine Labelle

发明人： Puneet Khanna ,  Dae-han Choi ,  Katherina Babich ,  Catherine Labelle

IPC分类号： H01L21/28

CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

摘要： Methods for fabricating integrated circuits using tailored chamfered gate liner profiles are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a dummy gate electrode overlying a semiconductor substrate and forming a liner on sidewalls of the dummy gate electrode. A dielectric material is deposited overlying the dummy gate electrode, the liner, and the substrate. The dummy gate electrode is exposed by chemical mechanical planarization. A portion of the dummy gate electrode is removed and the liner is isotropically etched such that it has a chamfered surface. A remainder of the dummy gate electrode is removed to form an opening that is filled with a metal.

摘要翻译： 提供了使用定制的倒角门衬垫轮廓制造集成电路的方法。 在一个示例性实施例中，一种用于制造集成电路的方法包括形成覆盖在半导体衬底上的伪栅电极，并在虚拟栅电极的侧壁上形成衬垫。 沉积在伪栅电极，衬垫和衬底上的电介质材料。 虚拟栅电极通过化学机械平面化曝光。 去除虚拟栅电极的一部分，并且将衬垫各向同性地蚀刻，使其具有倒角表面。 去除虚拟栅电极的其余部分以形成填充有金属的开口。