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1.发明授权公开(公告)号：US08748941B2
公开(公告)日：2014-06-10
申请号：US13372065
申请日：2012-02-13
IPC分类号： H01L29/66 , H01L29/20 , H01L29/423 , H01L29/872 , H01L29/778 , H01L29/417 , H01L29/06
CPC分类号： H01L29/7786 , H01L29/0619 , H01L29/0657 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/7787 , H01L29/872
摘要： A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer 124 sequentially formed on the substrate. The third nitride semiconductor layer contains p-type impurities, and is selectively formed between the first ohmic electrode and the Schottky electrode in contact with the Schottky electrode.
摘要翻译： 氮化物半导体器件包括形成在衬底上的半导体层，在半导体多层上彼此间隔开的第一欧姆电极和肖特基电极; 以及覆盖半导体多层的顶部的钝化膜。 半导体层叠体102包括顺序形成在基板上的第一氮化物半导体层，第二氮化物半导体层和p型第三氮化物半导体层124。 第三氮化物半导体层含有p型杂质，并且选择性地形成在与肖特基电极接触的第一欧姆电极和肖特基电极之间。
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公开(公告)号：US20120146093A1
公开(公告)日：2012-06-14
申请号：US13372065
申请日：2012-02-13
IPC分类号： H01L29/78
CPC分类号： H01L29/7786 , H01L29/0619 , H01L29/0657 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/7787 , H01L29/872
摘要： A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semiconductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer 102 includes a first nitride semiconductor layer, a second nitride semiconductor layer, and a p-type third nitride semiconductor layer 124 sequentially formed on the substrate. The third nitride semiconductor layer contains p-type impurities, and is selectively formed between the first ohmic electrode and the Schottky electrode in contact with the Schottky electrode.
摘要翻译： 氮化物半导体器件包括形成在衬底上的半导体层，在半导体多层上彼此间隔开的第一欧姆电极和肖特基电极; 以及覆盖半导体多层的顶部的钝化膜。 半导体层叠体102包括顺序形成在基板上的第一氮化物半导体层，第二氮化物半导体层和p型第三氮化物半导体层124。 第三氮化物半导体层含有p型杂质，并且选择性地形成在与肖特基电极接触的第一欧姆电极和肖特基电极之间。
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公开(公告)号：US08441035B2
公开(公告)日：2013-05-14
申请号：US13150574
申请日：2011-06-01
申请人： Masahiro Hikita , Hidetoshi Ishida , Tetsuzo Ueda
发明人： Masahiro Hikita , Hidetoshi Ishida , Tetsuzo Ueda
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/66462 , H01L29/808
摘要： The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.
摘要翻译： 本发明的目的是提供一种能够增加阈值电压以及降低导通电阻的FET和FET的制造方法。 本发明的FET包括第一未掺杂的GaN层; 形成在第一未掺杂的GaN层上的第一未掺杂的AlGaN层，其带隙能量大于第一未掺杂的GaN层的带隙能量; 形成在第一未掺杂的AlGaN层上的第二未掺杂的GaN层; 形成在所述第二未掺杂GaN层上的第二未掺杂AlGaN层，具有大于所述第二未掺杂GaN层的带隙能量的带隙能量; 形成在第二未掺杂AlGaN层的凹部中的p型GaN层; 形成在p型GaN层上的栅电极; 以及形成在所述栅电极的两个横向区域中的源电极和漏电极，其中在所述第一未掺杂的GaN层和所述第一未掺杂的AlGaN层之间的异质结界面处形成沟道。
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公开(公告)号：US07550821B2
公开(公告)日：2009-06-23
申请号：US11952407
申请日：2007-12-07
申请人： Daisuke Shibata , Kazushi Nakazawa , Masahiro Hikita , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Tsuyoshi Tanaka
发明人： Daisuke Shibata , Kazushi Nakazawa , Masahiro Hikita , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Tsuyoshi Tanaka
IPC分类号： H01L29/20
CPC分类号： H01L29/7786 , H01L21/76831 , H01L24/05 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L2224/05624 , H01L2224/05647 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/10329 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced apart from each other on an active region in the nitride semiconductor layer. An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface. A first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.
摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板的主表面上的氮化物半导体层，具有沟道区域，电子沿着与所述主表面平行的方向漂移的沟道区域; 以及在氮化物半导体层中的有源区上彼此隔开形成的多个第一电极和多个第二电极。 在氮化物半导体层上形成层间绝缘膜。 层间绝缘膜具有分别暴露第一电极并具有平坦化顶表面的开口。 第一电极焊盘形成在层间绝缘膜中的有源区上方的区域中，并且通过相应的开口与暴露的第一电极电连接。
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公开(公告)号：US20080149940A1
公开(公告)日：2008-06-26
申请号：US11952407
申请日：2007-12-07
申请人： Daisuke SHIBATA , Kazushi Nakazawa , Masahiro Hikita , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Tsuyoshi Tanaka
发明人： Daisuke SHIBATA , Kazushi Nakazawa , Masahiro Hikita , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Tsuyoshi Tanaka
IPC分类号： H01L29/205
CPC分类号： H01L29/7786 , H01L21/76831 , H01L24/05 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L2224/05624 , H01L2224/05647 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/10329 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced apart from each other on an active region in the nitride semiconductor layer. An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface. A first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.
摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板的主表面上的氮化物半导体层，具有沟道区域，电子沿着与所述主表面平行的方向漂移的沟道区域; 以及在氮化物半导体层中的有源区上彼此隔开形成的多个第一电极和多个第二电极。 在氮化物半导体层上形成层间绝缘膜。 层间绝缘膜具有分别暴露第一电极并具有平坦化顶表面的开口。 第一电极焊盘形成在层间绝缘膜中的有源区上方的区域中，并且通过相应的开口与暴露的第一电极电连接。
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公开(公告)号：US20120126290A1
公开(公告)日：2012-05-24
申请号：US13360275
申请日：2012-01-27
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7783
摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.
摘要翻译： 氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。 位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域 形成有具有比控制区域更高的电阻的高电阻区域。
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公开(公告)号：US20110297960A1
公开(公告)日：2011-12-08
申请号：US13213967
申请日：2011-08-19
CPC分类号： H01L29/7786 , H01L23/053 , H01L23/562 , H01L29/2003 , H01L29/225 , H01L29/452 , H01L29/475 , H01L2224/72 , H01L2924/01079 , H01L2924/12032 , H01L2924/00
摘要： A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer.
摘要翻译： 晶体管组件的制造方法包括以下步骤：（a）形成晶体管; （b）抛光基底; 和（c）将基底基板抛光的晶体管固定到支撑基板上。 步骤（a）是在基底基板的主表面上形成第一半导体层和第二半导体层的工序。 步骤（b）是对基材的与主面相反的表面进行研磨的工序。 步骤（c）是在施加到基底基板上的应力存在下，使晶体管固定在支撑基板上，使基板的翘曲减小的方向。 基底由不同于第一半导体层和第二半导体层的材料制成，并且在第二半导体层上施加拉伸应力。
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公开(公告)号：US07898002B2
公开(公告)日：2011-03-01
申请号：US11890480
申请日：2007-08-07
IPC分类号： H01L21/337 , H01L21/335
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。
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公开(公告)号：US07863649B2
公开(公告)日：2011-01-04
申请号：US12331668
申请日：2008-12-10
申请人： Masahiro Hikita , Tetsuzo Ueda
发明人： Masahiro Hikita , Tetsuzo Ueda
IPC分类号： H01L29/739
CPC分类号： H01L29/2003 , H01L29/1066 , H01L29/42316 , H01L29/7786 , H01L29/808
摘要： A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.
摘要翻译： 氮化物半导体器件包括：顺序地在衬底上形成的第一至第三氮化物半导体层。 第二氮化物半导体层的带隙能量大于第一氮化物半导体层的带隙能量。 第三氮化物半导体层具有开口。 形成p型第四氮化物半导体层，使得开口被填充。 在第四氮化物半导体层上形成栅电极。
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公开(公告)号：US20100327293A1
公开(公告)日：2010-12-30
申请号：US12880704
申请日：2010-09-13
IPC分类号： H01L29/20
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。
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