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    Thermal modulation system and method for locating a circuit defect
    1.
    发明授权
    Thermal modulation system and method for locating a circuit defect 失效
    用于定位电路缺陷的热调制系统和方法

    公开(公告)号：US06400128B2

    公开(公告)日：2002-06-04

    申请号：US09811884

    申请日：2001-03-19

    申请人： Daniel Guidotti ,  Arnold Halperin ,  Michael E. Scaman ,  Arthur R. Zingher

    发明人： Daniel Guidotti ,  Arnold Halperin ,  Michael E. Scaman ,  Arthur R. Zingher

    IPC分类号： G01R3102

    CPC分类号： G01R31/02 ,  G01R31/086

    摘要： A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined. Thus the system and method efficiently and accurately locates a defect in three dimensions, even if the workpiece is large, and the defect is small and underneath the surface.

    摘要翻译： 用于在诸如印刷电路板（PCB）或多芯片模块（MCM）的工件的电路中定位电路缺陷（例如短路或初始开路）的系统和方法。 该电路连接到用于敏感测量任何电阻变化的器件。 热刺激被施加到工件表面的各种子集，热刺激被时间调制，并且电阻变化测量与该调制相关。 通过应用精心设计的热刺激子集，可以在逻辑上组合对应于多个热刺激子集的电阻测量。 此外，可以迭代地改进可能位于缺陷处的搜索区域。 通过测量热刺激和相应的电阻变化之间的时间延迟，进一步确定了工件表面下方缺陷的深度。 因此，即使工件大，缺陷小，表面下方，系统和方法也能有效准确地定位三维缺陷。

    Thermal modulation system and method for locating a circuit defect such as a short or incipient open independent of a circuit geometry
    2.
    发明授权
    Thermal modulation system and method for locating a circuit defect such as a short or incipient open independent of a circuit geometry 失效
    用于定位电路缺陷的热调制系统和方法，例如短路或初始开路，独立于电路几何形状

    公开(公告)号：US06236196B1

    公开(公告)日：2001-05-22

    申请号：US09325472

    申请日：1999-06-03

    申请人： Daniel Guidotti ,  Arnold Halperin ,  Michael E. Scaman ,  Arthur R. Zingher

    发明人： Daniel Guidotti ,  Arnold Halperin ,  Michael E. Scaman ,  Arthur R. Zingher

    IPC分类号： G01R3102

    CPC分类号： G01R31/02 ,  G01R31/086

    摘要： A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined. Thus the system and method efficiently and accurately locates a defect in three dimensions, even if the workpiece is large, and the defect is small and underneath the surface.

    摘要翻译： 用于在诸如印刷电路板（PCB）或多芯片模块（MCM）的工件的电路中定位电路缺陷（例如短路或初始开路）的系统和方法。 该电路连接到用于敏感测量任何电阻变化的器件。 热刺激被施加到工件表面的各种子集，热刺激被时间调制，并且电阻变化测量与该调制相关。 通过应用精心设计的热刺激子集，可以在逻辑上组合对应于多个热刺激子集的电阻测量。 此外，可以迭代地改进可能位于缺陷处的搜索区域。 通过测量热刺激和相应的电阻变化之间的时间延迟，进一步确定了工件表面下方缺陷的深度。 因此，即使工件大，缺陷小，表面下方，系统和方法也能有效准确地定位三维缺陷。

    Method and apparatus for locating power plane shorts using polarized light microscopy
    3.
    发明授权
    Method and apparatus for locating power plane shorts using polarized light microscopy 失效
    使用偏光显微镜定位电源平面短路的方法和装置

    公开(公告)号：US6141093A

    公开(公告)日：2000-10-31

    申请号：US139515

    申请日：1998-08-25

    申请人： Bernell E. Argyle ,  Arnold Halperin ,  Michael E. Scaman ,  Edward J. Yarmchuk

    发明人： Bernell E. Argyle ,  Arnold Halperin ,  Michael E. Scaman ,  Edward J. Yarmchuk

    IPC分类号： G01N21/21 ,  G01R31/311 ,  G01N21/00 ,  G01R27/14

    CPC分类号： G01N21/21 ,  G01R31/311

    摘要： An apparatus and corresponding method for detecting, locating, or defining a short in a thin-film module. The apparatus includes a mechanical fixture supporting the module. A current source provides a current pulse to the module which produces a magnetic field and heating nearby the short which turns on and off as the pulsed current in the short turns on and off. Polarized light is directed onto the module, with an intermediate element disposed between the module and the source of the polarized light. The intermediate element may be a stress birefringent coating (e.g., a polyimide insulating layer) disposed on the module and onto which the polarized light is directed. The sample is rotated 0 to 45 degrees to maximize the birefringent effect. Alternatively, the intermediate element may be a magneto-optical Faraday rotator. A microscope is used to observe the module, facilitating identification of a short by the twisting of the polarization of the light as the short expands and shrinks in response to the heating or in response to the localized magnetic field. The preferred rotator is a composite having a garnet substrate, an iron garnet film disposed on the substrate, and a thin aluminum mirror layer disposed on the iron garnet film. The apparatus and method of the present invention have several applications.

    摘要翻译： 一种用于检测，定位或限定薄膜模块中的短路的装置和相应方法。 该装置包括支撑模块的机械夹具。 电流源向模块提供电流脉冲，其产生磁场并在短路附近加热，其短路中的脉冲电流接通和断开时导通和截止。 偏振光被引导到模块上，中间元件设置在模块和偏振光源之间。 中间元件可以是设置在模块上并且偏振光被引导到其上的应力双折射涂层（例如，聚酰亚胺绝缘层）。 样品旋转0至45度以最大化双折射效应。 或者，中间元件可以是磁光法拉第旋转器。 使用显微镜来观察模块，通过随着短路的扩展和响应于加热或响应于局部磁场而收缩，通过扭转光的偏振来促进短路的识别。 优选的旋转体是具有石榴石基材，设置在基材上的铁石榴石薄膜和设置在铁石榴石薄膜上的薄铝镜面层的复合体。 本发明的装置和方法有几个应用。

    Method for detecting power plane-to-power plane shorts and I/O net-to power plane shorts in modules and printed circuit boards
    5.
    发明授权
    Method for detecting power plane-to-power plane shorts and I/O net-to power plane shorts in modules and printed circuit boards 失效
    用于检测模块和印刷电路板中的电源平面到电源平面短路和I / O网络到电源平面短路的方法

    公开(公告)号：US06242923B1

    公开(公告)日：2001-06-05

    申请号：US09116396

    申请日：1998-07-16

    申请人： Michael E. Scaman ,  Edward J. Yarmchuk ,  Arnold Halperin

    发明人： Michael E. Scaman ,  Edward J. Yarmchuk ,  Arnold Halperin

    IPC分类号： G01R3128

    CPC分类号： G01R31/281 ,  G01R1/07314 ,  G01R31/025

    摘要： A method of locating in a non-destructive and non-invasive manner power plane-to-power plane shorts or I/O net-to-power plane shorts found in a printed circuit board or a multi-chip-module by way of a magnetic field generating probe is described. Thousands of nets can be simultaneously tested to detect not only the presence of a short but also to accurately pinpoint its position. For high resistance shorts, the probe is provided with a pot core housed inductor located at its tip, and is used at low frequencies to minimize the effect of the capacitive impedance between the power planes. For low resistance shorts, the probe is used at high frequencies, delivering equal but opposite current to each of two matched inductors at the tip of the probe to maximize mutual inductive coupling while minimizing electrostatic capacitive coupling with the board or module. In both cases, the highest current stress is on the probe rather than on the expensive and fragile package under inspection. This allows the test to be both more sensitive to high resistance shorts at low frequencies and is less destructive, thereby being less likely to blow filamentary shorts due to high current stresses through the board or module.

    摘要翻译： 以非破坏性和非侵入性的方式定位在印刷电路板或多芯片模块中通过以下方式发现的平面到电源平面短路或I / O网络至电源平面短路的方法 描述了磁场产生探针。 可以同时测试数千个网络，以检测不仅存在短路，还可以准确地确定其位置。 对于高电阻短路，探头设置有位于其尖端的锅芯容纳电感器，并且以低频率使用以最小化电力平面之间的电容性阻抗的影响。 对于低电阻短路，探头以高频率使用，为探头顶端的两个匹配电感器中的每一个提供相等但相反的电流，以最大化互感耦合，同时最小化与电路板或模块的静电电容耦合。 在这两种情况下，最高的电流应力在探头上，而不是昂贵和脆弱的被检查的包装。 这允许测试在低频下对高电阻短路更敏感，并且具有较小的破坏性，因此由于通过电路板或模块的高电流应力而不太可能发生短路短路。

    Contact Level Mask Layouts By Introducing Anisotropic Sub-Resolution Assist Features
    7.
    发明申请
    Contact Level Mask Layouts By Introducing Anisotropic Sub-Resolution Assist Features 审中-公开
    通过引入各向异性分解辅助功能的接触层面罩布局

    公开(公告)号：US20090191468A1

    公开(公告)日：2009-07-30

    申请号：US12021527

    申请日：2008-01-29

    申请人： Michael M. Crouse ,  Derren N. Dunn ,  Henning Haffner ,  Michael E. Scaman

    发明人： Michael M. Crouse ,  Derren N. Dunn ,  Henning Haffner ,  Michael E. Scaman

    IPC分类号： G03F1/00

    CPC分类号： G03F1/36

    摘要： This disclosure includes a SRAF layout that minimizes the number of SRAFs required to reliably print contact shapes. A method is provided that reduces the number of necessary SRAF features on a mask, placing at least two elongated SRAF shapes on the mask such that the elongated SRAF shapes extend past at least one edge of a mask shape in at least one direction.

    摘要翻译： 本公开包括SRAF布局，其最小化可靠地打印接触形状所需的SRAF的数量。 提供了一种减少掩模上必要的SRAF特征的数量的方法，在掩模上放置至少两个细长的SRAF形状，使得细长SRAF形状延伸经过至少一个方向上的掩模形状的至少一个边缘。

    ITERATIVE METHOD FOR REFINING INTEGRATED CIRCUIT LAYOUT USING COMPASS OPTICAL PROXIMITY CORRECTION (OPC)
    8.
    发明申请
    ITERATIVE METHOD FOR REFINING INTEGRATED CIRCUIT LAYOUT USING COMPASS OPTICAL PROXIMITY CORRECTION (OPC) 有权
    使用对比度校正（OPC）进行整合电路布局的迭代方法

    公开(公告)号：US20080141203A1

    公开(公告)日：2008-06-12

    申请号：US12033102

    申请日：2008-02-19

    申请人： Michael E. Scaman

    发明人： Michael E. Scaman

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.

    摘要翻译： 本发明是一种迭代方法或程序，涉及一系列光学邻近校正（OPC）处理步骤，用于在光刻工艺期间精炼晶片上的集成电路设计布局。 迭代方法可以应用为系统和计算机程序，以根据方向取向，选择边缘片段或非相对边缘片段的组合来分类和分组边缘片段，计算所选边缘片段的边缘放置误差和近端 移动边缘片段直到满足质量限制。

    Method and apparatus for detecting shorts in a multi-layer electronic package
    10.
    发明授权
    Method and apparatus for detecting shorts in a multi-layer electronic package 失效
    用于检测多层电子封装中的短路的方法和装置

    公开(公告)号：US5821759A

    公开(公告)日：1998-10-13

    申请号：US807076

    申请日：1997-02-27

    申请人： Michael E. Scaman ,  Edward J. Yarmchuk ,  Yuet-Ying Yu

    发明人： Michael E. Scaman ,  Edward J. Yarmchuk ,  Yuet-Ying Yu

    IPC分类号： G01R1/073 ,  G01R31/02 ,  G01R31/28

    CPC分类号： G01R31/281 ,  G01R1/07314 ,  G01R31/025

    摘要： A method and apparatus for locating shorts in multi-layer electronic packages during manufacture allows repair of the shorts and improved yields of the packages. A multi-layer package is fitted in a fixture after forming a thin film layer of metalization, and test is performed to detect shorts in the package. If a short is detected, a low current, high frequency signal is injected in pins on a bottom surface of the package. An approximate two dimensional location of the short is sensed by detecting an electromagnetic force induced by a magnetic field inductively coupled to a sensor proximate to the short on a top surface of the multi-layer package. The approximate location of the short is then inspected to precisely locate the short.

    摘要翻译： 在制造期间用于定位多层电子封装中的短路的方法和装置允许修复短路并提高封装的产量。 在形成金属化薄膜层之后，在夹具中装配多层封装，并进行测试以检测封装中的短路。 如果检测到短路，则将低电流，高频信号注入到封装底表面的引脚中。 通过检测由感应耦合到靠近多层封装的顶表面上的短路的传感器的磁场感应的电磁力来感测短路的近似二维位置。 然后检查短路的大致位置以精确定位短路。