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    Method of programming a non-volatile memory cell using a substrate bias
    1.
    发明授权
    Method of programming a non-volatile memory cell using a substrate bias 有权
    使用衬底偏置来编程非易失性存储单元的方法

    公开(公告)号：US06456536B1

    公开(公告)日：2002-09-24

    申请号：US09884409

    申请日：2001-06-19

    申请人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

    发明人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

    IPC分类号： G11C1604

    CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/12

    摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.

    摘要翻译： 一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。 该方法包括在栅极上施加恒定的第一电压，在第一区域上施加第二恒定电压，并向衬底施加恒定和负的第三电压，使得当与第三区域相比时，溢出电子的效应显着降低 不存在恒定电压。

    Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
    2.
    发明授权
    Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 有权
    使用负栅极擦除来增加具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的循环耐久性

    公开(公告)号：US06381179B1

    公开(公告)日：2002-04-30

    申请号：US09656675

    申请日：2000-09-07

    申请人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    发明人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    IPC分类号： G11C1604

    CPC分类号： G11C16/14 ,  G11C16/0416

    摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.

    摘要翻译： 通过使用初始负栅极擦除电压对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能。 通过利用负栅极擦除电压，随着编程擦除周期数的增加，单元不需要增加的擦除时间来减小单元阈值并避免不完全的擦除条件。

    Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
    3.
    发明授权
    Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效
    使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的擦除时间

    公开(公告)号：US06549466B1

    公开(公告)日：2003-04-15

    申请号：US09657143

    申请日：2000-09-07

    申请人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    发明人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    IPC分类号： G11C1604

    CPC分类号： G11C16/14

    摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.

    摘要翻译： 在擦除过程中通过使用负栅极擦除电压在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上执行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能 。 在擦除过程期间，应用擦除周期，随后读取周期，直到单元具有低于期望值的阈值。 对于程序中的初始擦除周期，施加初始负栅极电压。 在随后的擦除周期中，施加顺序减小的负栅极电压，直到阈值降低到期望值以下。 在一个实施例中，在擦除完成之后，施加的最后一个负栅极电压值被存储在单独的存储器中。 在再次施加擦除过程之后的后续编程之后，施加的初始负栅极电压是存储在存储器中的单元的负栅极电压值。

    Method of programming a non-volatile memory cell using a current limiter
    5.
    发明授权
    Method of programming a non-volatile memory cell using a current limiter 有权
    使用限流器对非易失性存储单元进行编程的方法

    公开(公告)号：US06269023B1

    公开(公告)日：2001-07-31

    申请号：US09694729

    申请日：2000-10-23

    申请人： Narbeh Derhacobian ,  Janet S. Y. Wang ,  Daniel Sobek ,  Sameer S. Haddad

    发明人： Narbeh Derhacobian ,  Janet S. Y. Wang ,  Daniel Sobek ,  Sameer S. Haddad

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

    摘要： A memory cell that includes a substrate that has a first region and a second region with a channel therebetween, wherein the first region generates hot carriers. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge. A current limiter that limits the number of the generated hot carriers that can flow into the channel, wherein the current limiter does not control the voltage of the second region.

    摘要翻译： 一种存储单元，包括具有第一区域的基板和在其间具有通道的第二区域，其中所述第一区域产生热载流子。 存储单元还包括通道上方的栅极和包含第一电荷量的电荷捕获区域。 限流器，其限制可流入通道的所产生的热载体的数量，其中限流器不控制第二区域的电压。

    Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure
    6.
    发明授权
    Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure 有权
    使用热载流子注入来控制具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元中的过度编程

    公开(公告)号：US06519182B1

    公开(公告)日：2003-02-11

    申请号：US09902332

    申请日：2001-07-10

    申请人： Narbeh Derhacobian ,  Daniel Sobek

    发明人： Narbeh Derhacobian ,  Daniel Sobek

    IPC分类号： G11C1604

    CPC分类号： G11C16/3486 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3468

    摘要： A programming operation using hot carrier injection is performed on a non volatile memory cell having an oxide-nitride-oxide structure by applying a first train of voltage pulses to he drain and a second train of voltage pulses to the gate. The programming method of the present invention prevents over-programming, minimizes programming time, and increases memory cell endurance and reliability.

    摘要翻译： 对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行使用热载流子注入的编程操作，通过向栅极施加第一列电压脉冲，将第二列电压脉冲施加到栅极。 本发明的编程方法防止过度编程，使编程时间最小化，并增加存储单元的耐久性和可靠性。

    Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
    7.
    发明授权
    Intelligent ramped gate and ramped drain erasure for non-volatile memory cells 有权
    非易失性存储单元的智能斜坡栅极和斜坡漏极擦除

    公开(公告)号：US06331953B1

    公开(公告)日：2001-12-18

    申请号：US09697813

    申请日：2000-10-26

    申请人： Janet S. Y. Wang ,  Narbeh Derhacobian ,  Daniel Sobek

    发明人： Janet S. Y. Wang ,  Narbeh Derhacobian ,  Daniel Sobek

    IPC分类号： G11C700

    CPC分类号： G11C16/344 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/14 ,  G11C16/3445 ,  H01L29/7923

    摘要： A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; and applying a voltage across the gate and the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.

    摘要翻译： 一种擦除存储单元的方法，该存储单元包括第一区域和第二区域以及通道之间的通道，以及包含第一电荷量的电荷捕获区域。 该方法包括：根据粗略擦除电压序列施加跨栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除; 以及根据电压的精细擦除序列施加跨越栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除。

    Method of simultaneous formation of bitline isolation and periphery oxide
    10.
    发明授权
    Method of simultaneous formation of bitline isolation and periphery oxide 有权
    同时形成位线隔离和周边氧化物的方法

    公开(公告)号：US06468865B1

    公开(公告)日：2002-10-22

    申请号：US09723653

    申请日：2000-11-28

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

    摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。