公开(公告)号：US06468865B1

公开(公告)日：2002-10-22

申请号：US09723653

申请日：2000-11-28

申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

公开(公告)号：US06555436B2

公开(公告)日：2003-04-29

申请号：US10223195

申请日：2002-08-19

申请人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

发明人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954 ,  Y10S438/981

摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

公开(公告)号：US06465306B1

公开(公告)日：2002-10-15

申请号：US09723635

申请日：2000-11-28

申请人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

发明人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954 ,  Y10S438/981

摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 并且在芯区域和周边区域中形成栅极。

公开(公告)号：US06465303B1

公开(公告)日：2002-10-15

申请号：US09885490

申请日：2001-06-20

申请人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

发明人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.

摘要翻译： 本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底， 包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

公开(公告)号：US06493261B1

公开(公告)日：2002-12-10

申请号：US09795865

申请日：2001-02-28

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

摘要翻译： 在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。 虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。 通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。

公开(公告)号：US06307784B1

公开(公告)日：2001-10-23

申请号：US09795856

申请日：2001-02-28

申请人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Kulachet Tanpairoj ,  Ravi Sunkavalli

发明人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Kulachet Tanpairoj ,  Ravi Sunkavalli

IPC分类号： G11C1600

CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

摘要： A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.

摘要翻译： 用于执行验证擦除的方法和系统包括对一个扇区中的每个I / O提供实质上高的电场的擦除脉冲。 该操作对于单个电源设备是重要的，因为整个阵列的擦除频带到带电流的开始大于由排水泵提供的带电流。 在第一个擦除脉冲之后，可以在所有IO上一起执行擦除验证程序。 在一个特定示例中，选择Vdrain电压处于基本上高的正电压，并且Vgate电压的值处于基本上高的负电压，其中Vdrain和Vgate之间的电压电位也是基本上高的电压。

公开(公告)号：US06442074B1

公开(公告)日：2002-08-27

申请号：US09795854

申请日：2001-02-28

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  G11C29/50

摘要： A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.

摘要翻译： 用于编程和擦除双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT和擦除脉冲进行编程来实现，该擦除脉冲为扇区1中的每个I / O提供基本上高的电场 一次 在第一个擦除脉冲之后，擦除验证程序在所有IO上一起执行。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 选择提供基本上高的电场的擦除脉冲，以消除整个阵列的频带电流，其大于由排水泵提供的频带电流。

公开(公告)号：US06233175B1

公开(公告)日：2001-05-15

申请号：US09693650

申请日：2000-10-21

申请人： Janet Wang ,  Ravi Sunkavalli

发明人： Janet Wang ,  Ravi Sunkavalli

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635

摘要： A method of programming flash EEPROM devices that provides self-limiting multi-level programming states. Each cell in the flash EEPROM device can be programmed to have one of multiple threshold voltages. Each cell to be programmed has a programming voltage applied to the gate, a programming voltage applied to the drain and bias voltage applied to either the source (Vs) or to the substrate (Vsub) or both. The bias voltages Vs or Vsub are determined during a precharacterization procedure and each desired threshold voltage has a corresponding bias voltage Vs or Vsub that provides the desired threshold voltage during the programming procedure. The bias voltages Vs or Vsub are selected to provide self-limiting programming by the effective vertical field Ev=Vg −Vt−(either Vs or Vsub), where Vt increases during programming until the programming stops. The lateral field El=Vd−(either Vs and/or Vsub) is adjusted during programming to keep the lateral field El equal to Vd.

摘要翻译： 编程提供自限制多级编程状态的闪存EEPROM器件的方法。 闪存EEPROM器件中的每个单元可以被编程为具有多个阈值电压之一。 要被编程的每个单元具有施加到栅极的编程电压，施加到漏极的编程电压和施加到源极（Vs）或衬底（Vsub）或两者的偏置电压。 偏置电压Vs或Vsub在预特性过程期间确定，并且每个期望的阈值电压具有在编程过程期间提供期望阈值电压的对应偏置电压Vs或Vsub。 选择偏置电压Vs或Vsub以通过有效垂直场Ev = Vg -Vt-（Vs或Vsub）提供自限制编程，其中Vt在编程期间增加直到编程停止。 在编程期间调整横向场El = Vd-（Vs和/或Vsub）以保持横向场El等于Vd。

公开(公告)号：US09208870B2

公开(公告)日：2015-12-08

申请号：US13615493

申请日：2012-09-13

申请人： Ravi Sunkavalli

发明人： Ravi Sunkavalli

IPC分类号： G11C13/00 ,  G11C8/16 ,  G11C7/10

CPC分类号： G11C13/003 ,  G11C7/1075 ,  G11C8/16 ,  G11C13/0002 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

摘要： A memory device can include at least two ports for transferring data to and from the memory device; and plurality of memory cells, each memory cell including at least one element programmable between different impedance states, and a plurality of access devices, each access device providing a current path between the element and a different one of the ports.

摘要翻译： 存储器设备可以包括用于将数据传送到存储器设备和从存储器设备传送数据的至少两个端口; 以及多个存储器单元，每个存储器单元包括在不同阻抗状态之间可编程的至少一个元件和多个存取器件，每个存取器件提供元件与不同端口之间的电流路径。

公开(公告)号：US08638138B2

公开(公告)日：2014-01-28

申请号：US12559040

申请日：2009-09-14

申请人： Ravi Sunkavalli ,  Rahul Nimaiyar ,  Ravi Kurlagunda ,  Vijay Bantval

发明人： Ravi Sunkavalli ,  Rahul Nimaiyar ,  Ravi Kurlagunda ,  Vijay Bantval

IPC分类号： H03L7/06

CPC分类号： G06F1/06 ,  G06F1/10

摘要： Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.

摘要翻译： 描述了用于形成和操作全局分层时钟树的方法，系统和电路。 全局分层时钟树可以包括时钟电路，其操作以向由时钟电路包围的核心电路提供时钟信号。 时钟电路可以包括分别产生第一和第二组时钟信号的两个或更多个第一和第二时钟发生器模块。 第一和第二时钟模块可以被定位成使得第一组时钟信号经历大致相等的第一延迟，并且第二组时钟信号经历大致相等的第二延迟。 公开了附加的方法，系统和电路。