公开(公告)号：US06489664B2

公开(公告)日：2002-12-03

申请号：US09866074

申请日：2001-05-24

Applicant: Danilo Re ,  Massimo Monselice ,  Paola Maria Granatieri

Inventor： Danilo Re ,  Massimo Monselice ,  Paola Maria Granatieri

IPC: H01L298605

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

Abstract translation: 描述了具有多晶硅电阻器的制造工艺和集成MOS器件。 该方法包括在单晶硅体顶部沉积多晶硅层; 在要制造电阻器的区域中在多晶硅层的顶部上形成氧化硅区域; 在多晶硅层顶部并与其接触形成金属硅化物层以形成双重导电层; 以及使导电层成形以形成MOS晶体管的栅极区域。 在双重导电层的蚀刻期间，去除氧化硅区域顶部的金属硅化物层，并且氧化硅区域形成下面的多晶硅的掩蔽区域，以形成具有比栅极更大的电阻率的电阻区域 地区。

公开(公告)号：US5793086A

公开(公告)日：1998-08-11

申请号：US772301

申请日：1996-12-23

Applicant: Emilio Giambattista Ghio ,  Giuseppe Meroni ,  Danilo Re ,  Livio Baldi

Inventor： Emilio Giambattista Ghio ,  Giuseppe Meroni ,  Danilo Re ,  Livio Baldi

IPC: G11C17/12 ,  H01L21/8238 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/112 ,  H01L29/78

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 在具有LDD单元的MOS或CMOS技术中制造的ROM存储器可以通过将已经形成的漏极区域与细胞的沟道区域去耦合而被有利地编程在相对较先进的制造阶段中，以通过将量子点 足以颠倒与沟道区相邻的漏极区的一部分中的导电性。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电性晶体管的源极/漏极区域的特意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至后期进行。

公开(公告)号：US5407852A

公开(公告)日：1995-04-18

申请号：US84971

申请日：1993-06-28

Applicant: Emilio G. Ghio ,  Giuseppe Meroni ,  Danilo Re ,  Livio Baldi

Inventor： Emilio G. Ghio ,  Giuseppe Meroni ,  Danilo Re ,  Livio Baldi

IPC: G11C17/12 ,  H01L21/8238 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/112 ,  H01L21/70

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 在具有LDD单元的MOS或CMOS技术中制造的ROM存储器可以通过将已经形成的漏极区域与细胞的沟道区域去耦合而被有利地编程在相对较先进的制造阶段中，以通过将量子点 足以颠倒与沟道区相邻的漏极区的一部分中的导电性。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电性晶体管的源极/漏极区域的特意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至后期进行。

公开(公告)号：US06261916B1

公开(公告)日：2001-07-17

申请号：US09209909

申请日：1998-12-11

Applicant: Danilo Re ,  Massimo Monselice ,  Paola Maria Granatieri

Inventor： Danilo Re ,  Massimo Monselice ,  Paola Maria Granatieri

IPC: H01L21283

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

公开(公告)号：US4703552A

公开(公告)日：1987-11-03

申请号：US689875

申请日：1985-01-09

Applicant: Livio Baldi ,  Giuseppe Corda ,  Giulio Iannuzzi ,  Danilo Re ,  Giorgio De Santi

Inventor： Livio Baldi ,  Giuseppe Corda ,  Giulio Iannuzzi ,  Danilo Re ,  Giorgio De Santi

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L29/4933 ,  H01L21/823835 ,  Y10S148/082

Abstract: The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.

Abstract translation: 该方法提供在多晶硅的栅极层上形成金属硅化物层，并且对于CMOS对的每个晶体管，同时掺杂有源区和栅极多晶硅。 在通过该方法制造的结构中，栅电极是由金属硅化物覆盖的多晶硅，并且n沟道晶体管的栅电极掺杂有n型材料，而p沟道晶体管的栅电极掺杂 p型杂质。 这使得即使在非常高的集成密度的情况下也可以为两个晶体管产生低阈值电压。

公开(公告)号：US5851871A

公开(公告)日：1998-12-22

申请号：US675520

申请日：1996-07-03

Applicant: Danilo Re

Inventor： Danilo Re

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/8242

CPC classification number: H01L28/40 ,  H01L21/8238 ,  H01L27/0688

Abstract: A process for manufacturing integrated capacitors in CMOS technology, comprising the steps of: producing, in a substrate of semiconductor material having a first type of conductivity, at least one well with the opposite type of conductivity, defining the active areas, producing insulation regions, depositing a first conducting layer of polycrystalline silicon adapted to form the gate regions and the lower plates of the capacitors, depositing a layer of silicon oxide at low temperature, to form the dielectric of the capacitors, depositing a second layer of polycrystalline silicon to form the second plate of the capacitors, shaping the polycrystalline silicon and silicon oxide layers, implanting and diffusing the source and drain regions of the CMOS transistors, providing the insulation layer, the metallic connecting layer, and final covering with a layer of protective insulation.

Abstract translation: 一种用于制造CMOS技术的集成电容器的方法，包括以下步骤：在具有第一类型导电性的半导体材料的衬底中制造具有相反导电性的至少一个阱，限定有源区，产生绝缘区， 沉积适于形成电容器的栅极区域和下部板的多晶硅的第一导电层，在低温下沉积氧化硅层，以形成电容器的电介质，沉积第二层多晶硅以形成 电容器的第二板，对多晶硅和氧化硅层进行成形，注入并扩散CMOS晶体管的源极和漏极区域，提供绝缘层，金属连接层以及具有保护绝缘层的最终覆盖层。

公开(公告)号：US5075246A

公开(公告)日：1991-12-24

申请号：US625764

申请日：1990-12-13

Applicant: Danilo Re ,  Alfonso Maurelli

Inventor： Danilo Re ,  Alfonso Maurelli

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L21/8221 ,  H01L21/823842 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11543 ,  H01L28/40 ,  Y10S148/014

Abstract: A method of manufacturing integrated circuits includes steps: forming a first layer of polycrystalline silicon on areas of a semiconductor substrate previously covered with a dielectric material; forming a first insulating layer and a second thin layer of polycrystalline silicon acting as a shield; removing the second layer of polycrystalline silicon and the first insulating layer except from predetermined areas for containing a first type of electronic component; doping the exposed portion of the first layer of polycrystalline silicon; forming, by deposition, masking and removal, of a second insulating layer on the first layer of polycrystalline silicon in an area for containing a second type of electronic component; forming of a third layer of polycrystalline silicon; masking predetermined zones of this latter layer lying at least partially above the areas intended for the two types of electronic components, and removing the polycrystalline silicon external to these predetermined zones. The method continues with conventional steps and makes it possible to obtain, for instance, EPROM memory cells and capacitors using the same polycrystalline silicon depositing steps for forming their electrodes, without dispensing with the maximum freedom and precision in the choice of the physical characteristics and dimensions of the two types of components.