公开(公告)号：US06567303B1

公开(公告)日：2003-05-20

申请号：US10050483

申请日：2002-01-16

申请人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

发明人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445

摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

摘要翻译： 提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。 因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。 此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

公开(公告)号：US07803680B2

公开(公告)日：2010-09-28

申请号：US11653649

申请日：2007-01-12

申请人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

发明人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

公开(公告)号：US20080171416A1

公开(公告)日：2008-07-17

申请号：US11653649

申请日：2007-01-12

申请人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

发明人： Shenging Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

公开(公告)号：US06287917B1

公开(公告)日：2001-09-11

申请号：US09392675

申请日：1999-09-08

申请人： Stephen Keetai Park ,  Tim Thurgate ,  Bharath Rangarajan

发明人： Stephen Keetai Park ,  Tim Thurgate ,  Bharath Rangarajan

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A process for fabricating an MNOS device includes the steps of forming a hardmask containing at least first and second openings over a core array area of a semiconductor substrate. An angle doping process is carried out to form halo regions in precise locations within the substrate at the edges of the first and second openings in the hardmask. Another doping process is carried out to form buried bit-lines in the substrate using the hardmask as a doping mask. Once the halo regions and the buried bit-lines are formed, the hardmask is removed and a composite dielectric layer is formed overlying the substrate. A gate layer is deposited to overlie the composite dielectric layer, and an etching process is carried out to form a control gate electrode and a charge storage electrode in the MNOS device

摘要翻译： 制造MNOS器件的方法包括以下步骤：在半导体衬底的芯阵列区域上形成至少包含第一和第二开口的硬掩模。 进行角度掺杂处理以在硬掩模中的第一和第二开口的边缘处在衬底内的精确位置中形成晕圈。 进行另一种掺杂工艺以使用硬掩模作为掺杂掩模在衬底中形成掩埋位线。 一旦形成了光晕区域和掩埋位线，就去除了硬掩模，并且在衬底上形成复合介电层。 沉积栅极层以覆盖复合介电层，并且进行蚀刻处理以在MNOS器件中形成控制栅电极和电荷存储电极

公开(公告)号：US07906395B2

公开(公告)日：2011-03-15

申请号：US12891481

申请日：2010-09-27

申请人： Shenqing Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

发明人： Shenqing Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分地蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

公开(公告)号：US08642441B1

公开(公告)日：2014-02-04

申请号：US11639667

申请日：2006-12-15

申请人： Tim Thurgate ,  Shenqing Fang ,  Kuo-Tung Chang ,  YouSeok Suh ,  Meng Ding ,  Hidehiko Shiraiwa ,  Amol Joshi ,  Harpreet Sachar ,  David Matsumoto ,  Lovejeet Singh ,  Chih-Yuh Yang

发明人： Tim Thurgate ,  Shenqing Fang ,  Kuo-Tung Chang ,  YouSeok Suh ,  Meng Ding ,  Hidehiko Shiraiwa ,  Amol Joshi ,  Harpreet Sachar ,  David Matsumoto ,  Lovejeet Singh ,  Chih-Yuh Yang

IPC分类号： H01L21/76

CPC分类号： H01L27/11563 ,  H01L21/28282 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/11568 ,  H01L29/66833

摘要： A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

摘要翻译： 公开了一种用于制造具有自对准陷阱层和圆形有源区域拐角的存储器件的方法。 在本发明中，在形成电荷捕获层和顶层之前进行STI工艺。 STI过程之后立即暴露有源区域的尖角。 因为这些尖角在这个时候被曝光，所以它们可以通过任何数量的已知的四舍五入技术进行四舍五入。 四舍五入改善了存储设备的性能特征。 在舍入处理之后，电荷捕获结构和其它层可以通过自对准工艺形成。

公开(公告)号：US07943980B2

公开(公告)日：2011-05-17

申请号：US12891532

申请日：2010-09-27

申请人： Shenqing Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

发明人： Shenqing Fang ,  Kuo-Tung Chang ,  Tim Thurgate ,  YouSeok Suh ,  Allison Holbrook

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

公开(公告)号：US09564331B2

公开(公告)日：2017-02-07

申请号：US13540373

申请日：2012-07-02

申请人： Shenqing Fang ,  Tung-Sheng Chen ,  Tim Thurgate ,  Di Li

发明人： Shenqing Fang ,  Tung-Sheng Chen ,  Tim Thurgate ,  Di Li

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L29/66 ,  H01L27/115 ,  H01L21/762

CPC分类号： H01L21/28282 ,  H01L21/76224 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

摘要翻译： 一种用于在闪速存储器件中连续成形的电荷俘获层形成的方法和装置。 存储器件包括包括源/漏区的半导体层。 隔离区域邻近源极/漏极区域设置。 第一绝缘体设置在源极/漏极区域的上方。 电荷捕获层设置在第一绝缘体内，其中电荷捕获层包括主体部分和在所述主体部分的任一侧上的第一尖端和第二尖端，其中所述电荷捕获层延伸超过源极/漏极的宽度 地区。 第二绝缘体设置在电荷捕获层上方。 多晶硅栅极结构设置在第二绝缘体上方，其中所述控制栅极的宽度比所述源极/漏极区域的宽度宽。

公开(公告)号：US06475816B1

公开(公告)日：2002-11-05

申请号：US09781435

申请日：2001-02-13

申请人： Concetta Riccobene ,  Nga-Ching Wong ,  Tim Thurgate

发明人： Concetta Riccobene ,  Nga-Ching Wong ,  Tim Thurgate

IPC分类号： H01L2166

CPC分类号： H01L22/14 ,  G01R31/27

摘要： A method is provided for accurately determining the junction depth of silicon-on-insulator (SOI) devices. Embodiments include determining the junction depth in an SOI device under inspection by measuring the threshold voltage of its “bottom transistor” formed by its source and drain regions together with its substrate acting as a gate. The threshold voltage of the bottom transistor of an SOI device varies with its junction depth in a predictable way. Thus, the junction depth of the inspected device is determined by comparing its bottom transistor threshold voltage with the bottom transistor threshold voltage of corresponding reference SOI devices of known junction depth to find a match. For example, simulated SOI devices with the same characteristics as the inspected device, whose junction depth and bottom transistor threshold voltages have been previously calculated, are used as a “reference library”. If the bottom transistor threshold voltage of the inspected device has about the same value as that of a particular one of the reference devices, then the inspected device has the junction depth of that particular reference device. Thus, junction depth of the inspected SOI device is accurately determined by a simple electrical measurement of threshold voltage.

摘要翻译： 提供了一种用于精确地确定绝缘体上硅（SOI）器件的结深度的方法。 实施例包括通过测量其源极和漏极区域形成的其“底部晶体管”及其衬底作为栅极的阈值电压来确定被检查的SOI器件中的结深度。 SOI器件的底部晶体管的阈值电压以其可预测的方式随其结深度而变化。 因此，通过将其底部晶体管阈值电压与已知结深度的相应参考SOI器件的底部晶体管阈值电压进行比较来确定被检查器件的结深度以找到匹配。 例如，具有与被预先计算的结深度和底部晶体管阈值电压的被检查器件相同特性的模拟SOI器件被用作“参考库”。 如果被检查装置的底部晶体管阈值电压具有与特定参考装置的底部晶体管阈值电压相同的值，则所检查的装置具有该特定参考装置的结深度。 因此，通过阈值电压的简单电测量精确地确定被检查的SOI器件的结深度。

公开(公告)号：US06452840B1

公开(公告)日：2002-09-17

申请号：US09693649

申请日：2000-10-21

申请人： Ravi S. Sunkavalli ,  Lee Cleveland ,  Sameer S. Haddad ,  Richard Fastow ,  Tim Thurgate

发明人： Ravi S. Sunkavalli ,  Lee Cleveland ,  Sameer S. Haddad ,  Richard Fastow ,  Tim Thurgate

IPC分类号： G11C1604

CPC分类号： G11C16/3477 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3472

摘要： A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the erase vertical electrical field that is to be applied to the array. The vertical electrical field is adjusted by changing the gate voltage, the well voltage or changing both simultaneously.

摘要翻译： 一种擦除闪速存储器件的方法，其提高可靠性并减少擦除速度的降低。 在擦除阶段或验证阶段期间确定擦除状态，并将信息反馈到调整要应用于阵列的擦除垂直电场的控制器。 通过改变栅极电压，井电压或同时改变两者来调节垂直电场。