公开(公告)号：US07038950B1

公开(公告)日：2006-05-02

申请号：US10982296

申请日：2004-11-05

申请人： Darlene Hamilton ,  Ed Hsia ,  Pau-Ling Chen

发明人： Darlene Hamilton ,  Ed Hsia ,  Pau-Ling Chen

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/349 ,  G11C2211/5621

摘要： Methods of programming NEW data into unprogrammed bits of a group of memory cells is provided. The method applies an interactive programming algorithm that individually verifies and programs the NEW data, reference (REF) data, and existing or OLD data. OLD data is separately verified to a compensated program verify level from that of the NEW data to improve memory reliability and insure minimal uniform stress levels to the array. The improved programming algorithm prevents older data from being needlessly refreshed, thus mitigating stress to the cells that eventually causes the data areas to decay at different rates and become prematurely unreliable.

摘要翻译： 提供将新数据编程到一组存储器单元的未编程位中的方法。 该方法应用一种交互式编程算法，可以对新数据，参考（REF）数据和现有或OLD数据进行单独验证和编程。 OLD数据被分别验证为与NEW数据的补偿程序验证级别，以提高内存可靠性并确保阵列的最小均匀应力水平。 改进的编程算法防止老化的数据被不必要地刷新，从而减轻细胞的压力，最终导致数据区域以不同的速率衰减并变得过早地不可靠。

公开(公告)号：US06791880B1

公开(公告)日：2004-09-14

申请号：US10431320

申请日：2003-05-06

申请人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

发明人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

IPC分类号： G11C1606

CPC分类号： G11C29/026 ,  G11C16/04 ,  G11C16/349 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006

摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

摘要翻译： 具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。 包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源 参考电流源。 来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。 可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流 或骑自行车。

公开(公告)号：US07076703B1

公开(公告)日：2006-07-11

申请号：US10305700

申请日：2002-11-26

申请人： Binh Quang Le ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Pau-Ling Chen

IPC分类号： G11C29/00

CPC分类号： G11C29/804

摘要： A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.

摘要翻译： 一种用于存储器冗余的方法，包括通常具有存储器单元的多个列（例如，位线）的存储器阵列，以及识别存储器阵列的特定（例如，有缺陷的）列，并进一步通过选择一个 一组相邻列，包括有缺陷的列。 所选列组中的列数可以等于耦合到存储器阵列的冗余阵列中的列数。 冗余阵列用于存储否则将存储在冗余窗口中的存储器单元中的信息。 所选择的组包括在缺陷列的一侧上的至少一个列和在缺陷列的另一侧上的另一个列。 通常，有缺陷的列的每一侧将有多个列。

公开(公告)号：US06622201B1

公开(公告)日：2003-09-16

申请号：US09525078

申请日：2000-03-14

申请人： Michael VanBuskirk ,  Pau-Ling Chen

发明人： Michael VanBuskirk ,  Pau-Ling Chen

IPC分类号： G06F1200

CPC分类号： G11C7/22

摘要： A sequential access memory structure includes an output bus and a plurality of sequential access memories, each of which is connected to the output bus. Each memory includes a memory array having a plurality of sequentially readable memory elements, a carry output for producing a carry signal when reading of the array has been substantially completed, and a carry input for causing reading of the array in response to a carry signal. The carry output of each memory is connected to a carry input of one other downstream memory respectively in a chain arrangement, and the carry signals cause the arrays to be read sequentially onto the output bus. Each memory further comprises a read-write storage connected between the array and the output bus, the storage including a plurality of sections. Data from the array is loaded into one section of the storage while data is being read from another section of the storage onto the output bus. The sections of memory elements in the array comprise half-pages. The storage comprises two sections, each of which has a half-page of memory elements, and the carry output produces the carry signal prior to reading data from a last half-page of the array out of the storage onto the output bus. Data from the last half-page is read onto the output bus while data from a first half-page of an array of a next downstream memory is being loaded into its storage.

摘要翻译： 顺序访问存储器结构包括输出总线和多个顺序存取存储器，每个存取存储器连接到输出总线。 每个存储器包括具有多个可顺序读取的存储器元件的存储器阵列，当阵列的读取已基本完成时用于产生进位信号的进位输出，以及用于响应于进位信号而引起阵列读取的进位输入。 每个存储器的进位输出分别以链排列连接到另一个下游存储器的进位输入，并且进位信号使得阵列被顺序读取到输出总线上。 每个存储器还包括连接在阵列和输出总线之间的读写存储器，存储器包括多个部分。 来自阵列的数据被加载到存储的一部分中，同时从存储器的另一部分读取数据到输出总线上。 阵列中的内存元素部分包括半页。 存储器包括两个部分，每个部分具有半页存储器元件，并且进位输出在从阵列的最后半页从存储器中读取数据到输出总线之前产生进位信号。 来自上一个半页的数据被读取到输出总线上，而来自下一个下游存储器阵列的前半页的数据被加载到其存储器中。

公开(公告)号：US06510082B1

公开(公告)日：2003-01-21

申请号：US09999869

申请日：2001-10-23

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/28

摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

摘要翻译： 公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。 该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线， 其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。 该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流 在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

公开(公告)号：US06373742B1

公开(公告)日：2002-04-16

申请号：US09689036

申请日：2000-10-12

申请人： Kazuhiro Kurihara ,  Shane C. Hollmer ,  Pau-Ling Chen

发明人： Kazuhiro Kurihara ,  Shane C. Hollmer ,  Pau-Ling Chen

IPC分类号： G11C506

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C5/063

摘要： A decoder for decoding from two sides of a memory array. The decoder is positioned on two sides of the memory array. The decoder includes driver circuits that are connected to routing lines from the memory array. To reduce the size of the decoder, some of the routing lines extend from one side of the memory array and the remaining routing lines extend from the other side of the memory array.

摘要翻译： 一种用于从存储器阵列的两侧进行解码的解码器。 解码器位于存储器阵列的两侧。 解码器包括从存储器阵列连接到路由线路的驱动器电路。 为了减小解码器的大小，一些路由线从存储器阵列的一侧延伸，并且剩余的路由线从存储器阵列的另一侧延伸。

公开(公告)号：US06288951B1

公开(公告)日：2001-09-11

申请号：US09675940

申请日：2000-09-29

申请人： Pau-Ling Chen ,  Binh Quang Le

发明人： Pau-Ling Chen ,  Binh Quang Le

IPC分类号： G11C700

CPC分类号： G11C5/145

摘要： A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage.

摘要翻译： 一种非易失性存储器和方法，用于在目标输出电压下长时间持续地调节非易失性存储器的电荷泵的输出。

公开(公告)号：US06262469B1

公开(公告)日：2001-07-17

申请号：US09047237

申请日：1998-03-25

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

IPC分类号： H01L2900

CPC分类号： H01L29/94 ,  H01L27/0811 ,  H01L29/66189

摘要： A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.

摘要翻译： 电容器分压器包括两个电容器，它们串联在两个电压源之间。 第一电容器是浮置栅极电容器，其中一个板是浮栅晶体管结构的控制栅极，另一个栅极是浮栅晶体管结构的源极，漏极和沟道区。 电容分压器的优点是具有至少一个浮置栅极电容器，可以在电压调节器中实现，并且可以用于跨越电容器的各种电压。

公开(公告)号：US6146944A

公开(公告)日：2000-11-14

申请号：US39783

申请日：1998-03-16

申请人： Yue-Song He ,  Che-Hoo Ng ,  Pau-Ling Chen

发明人： Yue-Song He ,  Che-Hoo Ng ,  Pau-Ling Chen

IPC分类号： H01L21/265 ,  H01L21/8247

CPC分类号： H01L27/11517 ,  H01L21/26586

摘要： A P-type dopant is implanted into a substrate region 94 under a select drain gate transistor field oxide region 75 at a large tilt angle .alpha., to prevent field turn-on under the select drain gate transistor field oxide region 75 in a non-volatile memory device such as a NAND flash memory device. A substrate region 114 under a select source gate transistor field oxide region 77 can also be implanted with a P-type dopant to prevent field turn-on under the region 77 if select source gates 90 and 92 are to be supplied with a voltage in operation rather than grounded. The substrate regions 94 and 114 under both the select drain gate transistor field oxide region 75 and the select source gate transistor field oxide region 77 can be implanted with the P-type dopant using a fixed-angle ion beam 120, by rotating the wafer 124 between the step of implanting one of the substrate regions and the step of implanting the other region.

摘要翻译： P型掺杂剂以大的倾斜角α被注入到选择漏极栅极晶体管场氧化物区域75下方的衬底区域94中，以防止选择漏极栅极晶体管场氧化物区域75在非易失性 诸如NAND闪存器件的存储器件。 选择源栅极晶体管场氧化物区域77下方的衬底区域114也可以注入P型掺杂剂，以防止在选择源极栅极90和92被施加电压时在区域77下的场导通 而不是接地。 在选择漏极栅极晶体管场氧化物区域75和选择源极栅极晶体管场氧化物区域77两者之下的衬底区域94和114可以使用固定角度离子束120注入P型掺杂剂，通过旋转晶片124 在植入一个衬底区域的步骤和植入另一个区域的步骤之间。

公开(公告)号：US5999452A

公开(公告)日：1999-12-07

申请号：US63688

申请日：1998-04-21

申请人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。