利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.017 秒)

    Modulation of line-select times of individual rows of a flat-panel display for gray-scaling
    1.
    发明授权
    Modulation of line-select times of individual rows of a flat-panel display for gray-scaling 失效
    对平板显示器的各行的行选择时间进行调整，以进行灰度调整

    公开(公告)号：US6057809A

    公开(公告)日：2000-05-02

    申请号：US82003

    申请日：1998-05-20

    申请人： Dave M. Singhal ,  Chester F. Bassetti

    发明人： Dave M. Singhal ,  Chester F. Bassetti

    IPC分类号： G06F3/14 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/18 ,  G09G5/36 ,  H03L7/07 ,  H05K9/00

    CPC分类号： G09G3/2018 ,  H03L7/07 ,  H05K9/0069 ,  G06F3/1475 ,  G09G2310/08 ,  G09G2330/06 ,  G09G3/3644

    摘要： The amount of time that a row of pixels in a flat-panel display is illuminated is modulated from frame-to-frame and from row-to-row. Pixels in rows that are on for a longer period of time appear brighter than pixels in rows that are on for shorter periods of time. Such line modulation is combined with frame-rate-cycling (FRC) to dramatically increase the number of gray scales that can be generated for any given number of frames in a FRC cycle, and with phase-offsetting to keep the frame period constant and to reduce flicker. An N-frame FRC cycle that previously generated N+1 gray scales now produces a full 2.sup.N gray scales. The total pixel-on time over the N frame cycle depends not just on how many frames the pixel is on, but on which frames the pixel is on. Since each row in each frame in the FRC cycle is on for a different amount of time, aliasing of the frames is greatly lessened or no longer occurs. A line modulation buffer and speeding up the pixel clock to the panel allow for greater modulation.

    摘要翻译： 平面显示器中的一行像素被照亮的时间量从帧到帧和从一行到另一行调制。 在较长时间内打开的行中的像素显示比较短时间段内的行中的像素更亮。 这种线路调制与帧速率循环（FRC）组合，以显着增加在FRC周期中任何给定数量的帧可以产生的灰度数，并且通过相位偏移来保持帧周期恒定，并且 减少闪烁。 以前产生N + 1灰度级的N帧FRC周期现在产生完整的2N灰度级。 N帧周期上的总像素开启时间不仅取决于像素所在的帧数，而且取决于像素在哪个帧上。 由于FRC周期中每帧中的每行开启不同的时间量，所以帧的混叠大大减少或不再发生。 线路调制缓冲器并将像素时钟加速到面板允许更大的调制。

    Multiple concurrent display system
    4.
    发明授权
    Multiple concurrent display system 失效
    多并发显示系统

    公开(公告)号：US5488385A

    公开(公告)日：1996-01-30

    申请号：US206010

    申请日：1994-03-03

    申请人： Dave M. Singhal ,  Sidong Li

    发明人： Dave M. Singhal ,  Sidong Li

    IPC分类号： G06F3/14 ,  G09G3/36 ,  G09G5/39 ,  G09G5/395 ,  G09G5/12

    CPC分类号： G09G5/395 ,  G06F3/1431 ,  G09G3/3644 ,  G09G5/39

    摘要： Video information is simultaneously generated for presentation on multiple displays by a display system including a video memory having a plurality of addressable storage locations, each storage location providing for the storage of data representing a component of an independent displayable image and a video controller providing a plurality of output display control and data signals connectable to a respective plurality of video displays. The video controller accesses the video memory in a predetermined addressing pattern so as to access a sequence of the components corresponding to a plurality of the independent displayable images. The video controller, in turn, generates the plurality of output display control and data signals whereby the sequence of the components provided by way of each of the plurality of the output display control and data signals corresponds to a respective one of the independent displayable images.

    摘要翻译： 同时产生视频信息，用于通过包括具有多个可寻址存储位置的视频存储器的显示系统在多个显示器上呈现，每个存储位置提供用于存储表示独立可显示图像的分量的数据，以及提供多个 的输出显示控制和可连接到相应的多个视频显示器的数据信号。 视频控制器以预定的寻址模式访问视频存储器，以便访问对应于多个独立可显示图像的部件的序列。 视频控制器又产生多个输出显示控制和数据信号，由此通过多个输出显示控制和数据信号中的每一个提供的组件序列对应于独立可显示图像中的相应一个。

    Methods for transforming streaming video data
    5.
    发明授权
    Methods for transforming streaming video data 失效
    转换流视频数据的方法

    公开(公告)号：US07339993B1

    公开(公告)日：2008-03-04

    申请号：US09502549

    申请日：2000-02-10

    申请人： Roger K. Brooks ,  Stephen A. Molloy ,  Chi-Te Feng ,  Qing Zhang ,  Yanda Ma ,  Dave M. Singhal

    发明人： Roger K. Brooks ,  Stephen A. Molloy ,  Chi-Te Feng ,  Qing Zhang ,  Yanda Ma ,  Dave M. Singhal

    IPC分类号： H04N7/12 ,  H04N11/02

    CPC分类号： H04L65/605 ,  H04L65/80 ,  H04N7/0127 ,  H04N7/0135 ,  H04N21/440263 ,  H04N21/440281

    摘要： A method for forming an output stream of data includes determining an output resolution for the output stream of data, determining an output frame rate for the output stream of data, determining an output color depth for the output stream of data, retrieving a first frame of data, a second frame of data, and a third frame of data from an input stream of data, the input stream of data having an input resolution, an input frame rate, and an input color depth, subsampling the first frame of data, the second frame of data, and the third frame of data to respectively form a first subsampled frame of data, a second subsampled frame of data, and a third subsampled frame of data, when the output resolution is lower than the input resolution, dropping the second subsampled frame of data, when the output frame rate is lower than the input frame rate, reducing color depth for the first subsampled frame of data and the second subsampled frame of data to respectively form a first reduced frame of data and a second reduced frame of data, when the output color depth is smaller than the input color depth, and converting the first reduced frame of data and the second reduced frame of data into the output stream of data.

    摘要翻译： 用于形成输出数据流的方法包括确定数据的输出流的输出分辨率，确定输出数据流的输出帧速率，确定输出数据流的输出颜色深度，检索数据的第一帧 数据，第二帧数据和来自输入数据流的第三帧数据，所述输入数据流具有输入分辨率，输入帧速率和输入颜色深度，对第一数据帧进行二次采样， 第二帧数据和第三帧数据分别形成数据的第一子采样帧，第二子采样帧数据和第三子采样帧数据，当输出分辨率低于输入分辨率时，丢弃第二帧数据 子采样数据帧，当输出帧速率低于输入帧速率时，减少第一子采样帧数据的色深和第二子采样帧数据，分别形成d的第一缩减帧 并且当输出颜色深度小于输入颜色深度时，将数据的第一缩小帧和第二缩小的数据帧转换成输出数据流。

    Low power clocking apparatus and method
    6.
    发明授权
    Low power clocking apparatus and method 失效
    低功率计时装置及方法

    公开(公告)号：US5467042A

    公开(公告)日：1995-11-14

    申请号：US149107

    申请日：1993-11-08

    申请人： Stephen A. Smith ,  Bryan Richter ,  Dave M. Singhal

    发明人： Stephen A. Smith ,  Bryan Richter ,  Dave M. Singhal

    IPC分类号： G06F1/32 ,  H03K3/00

    CPC分类号： G06F1/3287 ,  G06F1/3203 ,  Y02B60/1282

    摘要： A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.

    摘要翻译： 低功率计时装置和方法被用于通过经配置以选择性地从电子系统或集成电路发送或接收信号的系统总线来耦合到外部系统的电子系统或集成电路来降低功耗。 电子系统或集成电路包括多个子电路。 每个子电路被配置为在时钟信号的控制下操作，并且还包括用于保持或拒绝时钟信号的装置。 一旦电子系统或集成电路中的每个子电路拒绝时钟信号，整数仲裁电路将时钟信号禁止所有子电路。 仲裁器电路连续监视系统总线。 在检测到子电路需要时钟信号时，仲裁器将重新使能到所有子电路的时钟信号。

    Method and apparatus for controlling a mixed voltage interface in a multivoltage system
    7.
    发明授权
    Method and apparatus for controlling a mixed voltage interface in a multivoltage system 失效
    用于控制多电压系统中的混合电压接口的方法和装置

    公开(公告)号：US5440244A

    公开(公告)日：1995-08-08

    申请号：US149061

    申请日：1993-11-08

    申请人： Bryan M. Richter ,  Stephen A. Smith ,  Mike Assar ,  Abdul Q. Kashmiri ,  Jerry L. Clark ,  Dave M. Singhal

    发明人： Bryan M. Richter ,  Stephen A. Smith ,  Mike Assar ,  Abdul Q. Kashmiri ,  Jerry L. Clark ,  Dave M. Singhal

    IPC分类号： H01L27/118 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/0175

    CPC分类号： H01L27/11898 ,  H03K19/0027 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/018585 ,  H03K19/018592 ,  H03K2217/0018

    摘要： The design and implementation of a low power CMOS bi-directional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The buffer further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels. An multivoltage I/O buffer having multiple input-receiving NOR gates is also described. The NOR gates of the multivoltage I/O buffer having triggering levels optimized for differing core voltage levels. Also described is a host adapted system for interfacing between and removable peripheral card and a host computer. The host adaptor includes an integrated circuit employing the multivoltage bi-directional I/O buffer.

    摘要翻译： 低功耗CMOS双向I / O缓冲器的设计和实现，将低电压核心逻辑电平信号转换为最高逻辑电平信号，以驱动输出可选逻辑电平信号的最终输出级。 缓冲器还将各种逻辑电平的输入信号转换为低电压核心逻辑电平信号。 在任一情况下，在需要电压转换来表示适当的二进制逻辑电平的混合电源环境中AC和DC功耗被最小化。 还描述了具有多个输入接收NOR门的多电压I / O缓冲器。 具有针对不同核心电压电平优化的触发电平的多电压I / O缓冲器的或非门。 还描述了用于在可移动外围卡和主计算机之间进行接口的主机适配系统。 主机适配器包括采用多电压双向I / O缓冲器的集成电路。

    Personal broadcasting and viewing method of audio and video data using a wide area network
    9.
    发明授权
    Personal broadcasting and viewing method of audio and video data using a wide area network 有权
    使用广域网的个人广播和视听数据的观看方法

    公开(公告)号：US07069573B1

    公开(公告)日：2006-06-27

    申请号：US09539492

    申请日：2000-03-30

    申请人： Roger K. Brooks ,  Yanda Ma ,  Dave M. Singhal

    发明人： Roger K. Brooks ,  Yanda Ma ,  Dave M. Singhal

    IPC分类号： H04N7/16 ,  H04N7/173

    CPC分类号： H04N21/25858 ,  H04N7/17336 ,  H04N21/25883 ,  H04N21/25891 ,  H04N21/47202 ,  H04N21/4755 ,  H04N21/812 ,  H04N21/8193

    摘要： A method for transmitting audio/video data from a web site to viewing devices, e.g., personal digital assistant, cellular phone. The method includes prompting at least two selections on a viewing device, which is coupled to a worldwide network of computers through a wireless connection. The two selections comprises a first selection for an automatic set up (441) and a second selection for a manual set up. The method includes selecting either the first selection or the second selection and transmitting the selection to a web site, which is coupled to a source of audio/video data, e.g., camera. If the first selection is entered, a web page based upon a viewer's profile of the viewing device is formed and transmitted to the viewing device. Alternatively, if the second selection is entered, a form page of selectable parameters is formed and transmitted from the web site to the viewing device. Next, audio/video data from the web site is transmitted to the viewing device based upon the first selection or the second selection.

    摘要翻译： 用于将音频/视频数据从网站发送到诸如个人数字助理，蜂窝电话的观看设备的方法。 该方法包括在观看设备上提示至少两个选择，其通过无线连接耦合到全球计算机网络。 这两个选择包括用于自动设置（441）的第一选择和用于手动设置的第二选择。 该方法包括选择第一选择或第二选择，并将选择发送到与音频/视频数据源（例如相机）耦合的网站。 如果输入了第一选择，则形成基于查看器的查看器的配置文件的网页并将其发送到观看设备。 或者，如果输入第二选择，则形成可选参数的表单页并从网站发送到观看设备。 接下来，基于第一选择或第二选择将来自网站的音频/视频数据发送到观看设备。

    Personal broadcasting system for audio and video data using a wide area network
    10.
    发明授权
    Personal broadcasting system for audio and video data using a wide area network 有权
    使用广域网的音频和视频数据的个人广播系统

    公开(公告)号：US07047305B1

    公开(公告)日：2006-05-16

    申请号：US09539193

    申请日：2000-03-30

    申请人： Roger K. Brooks ,  Yanda Ma ,  Dave M. Singhal ,  Xia Hong

    发明人： Roger K. Brooks ,  Yanda Ma ,  Dave M. Singhal ,  Xia Hong

    IPC分类号： G06F15/16 ,  H04N3/16 ,  H04N5/257 ,  H04N5/76 ,  H04N7/16

    CPC分类号： H04L29/06027 ,  H04L65/607 ,  H04N7/17318 ,  H04N21/234363 ,  H04N21/23439 ,  H04N21/25825 ,  H04N21/25883 ,  H04N21/25891 ,  H04N21/2662 ,  H04N21/2743 ,  H04N21/41407 ,  H04N21/4223

    摘要： A system for transferring real time video information from a source device to one of a plurality of output devices includes an image capturing device for acquiring video information, the image capturing device comprising a processor, a graphics module coupled to the processor, a browsing device coupled to the processor, a packetizing portion coupled to the processor, the packetizing portion being adapted to convert the video information into a packetized stream of information, the packetized stream of information being in a first format, and an output device coupled to the processor for transferring the packetized stream of information to a network, a network gateway coupled to the image capturing device through the network, the network gateway being coupled to a worldwide network of computers, the network gateway comprising a gateway transcoding device for converting the packetized stream of information from the first format to a second format, the network gateway also comprising a packetizing portion for transferring the packetized stream of information in the second format to the network, and a display device coupled to the network gateway through the world wide network of computers, the display device comprising a display device for converting the packetized stream of information into video information for display, the display device also comprising a display for displaying the video information on the display device.

    摘要翻译： 用于将实时视频信息从源设备传送到多个输出设备之一的系统包括用于获取视频信息的图像捕获设备，所述图像捕获设备包括处理器，耦合到所述处理器的图形模块，耦合到所述处理器的浏览设备 所述分组化部分适于将所述视频信息转换为分组信息流，所述分组化信息流为第一格式，以及耦合到所述处理器的输出设备，用于传送 信息流到网络，网络网关通过网络耦合到图像捕获设备，网络网关耦合到全球计算机网络，网络网关包括网关转码设备，用于将分组化的信息流从 第一格式到第二格式，网关还包括一个pa 用于将第二格式的分组化信息流传送到网络，以及通过全球计算机网络耦合到网络网关的显示设备，该显示设备包括用于将分组化的信息流转换成视频的显示设备 显示装置还包括用于在显示装置上显示视频信息的显示器。