公开(公告)号：US5823339A

公开(公告)日：1998-10-20

申请号：US686901

申请日：1996-07-25

申请人： David A. Dunham ,  Robert G. Haskett ,  Paul Dennis Owings ,  Henry Louis Tew ,  Jeffrey B. Davis ,  Christopher E. Jacob ,  Maureen Wolthuis

发明人： David A. Dunham ,  Robert G. Haskett ,  Paul Dennis Owings ,  Henry Louis Tew ,  Jeffrey B. Davis ,  Christopher E. Jacob ,  Maureen Wolthuis

IPC分类号： B65D5/50 ,  B65D71/08

CPC分类号： B65D5/5038 ,  B65D5/5009

摘要： A container has a back wall, a pair of opposing side walls extending from the back wall, and a front wall extending between the side walls to define a rectangular sleeve. Apertures are formed in the front wall to enable access within the sleeve. The apertures are separated from one another by a front wall portion. Also, a top and bottom band are formed at the ends of the container. At least one positioning member extends from the front wall. The positioning member extends toward the back wall to maintain an article in position within the container.

摘要翻译： 容器具有后壁，从后壁延伸的一对相对侧壁和在侧壁之间延伸以限定矩形套筒的前壁。 在前壁中形成孔径以使得能够在套筒内进入。 孔通过前壁部分彼此分离。 另外，顶部和底部带形成在容器的端部。 至少一个定位构件从前壁延伸。 定位构件朝向后壁延伸，以将物品保持在容器内的适当位置。

公开(公告)号：US06369553B1

公开(公告)日：2002-04-09

申请号：US09539374

申请日：2000-03-31

申请人： Jeffrey B. Davis

发明人： Jeffrey B. Davis

IPC分类号： G05F140

CPC分类号： G05F1/465

摘要： An apparatus and a method for decreasing the voltage from a source. The apparatus includes a voltage reference source. The voltage reference source is coupled to a first transistor and to a decoupling capacitor. The first transistor is a negative-channel metal oxide (“NMOS”) transistor which has an output voltage equal to a gate source voltage of the NMOS transistor minus an NMOS transistor threshold voltage.

摘要翻译： 一种降低源极电压的装置和方法。 该装置包括电压基准源。 电压参考源耦合到第一晶体管和去耦电容器。 第一晶体管是具有等于NMOS晶体管的栅极源极电压的输出电压减去NMOS晶体管阈值电压的负极沟道金属氧化物（“NMOS”）晶体管。

公开(公告)号：US06163199A

公开(公告)日：2000-12-19

申请号：US240544

申请日：1999-01-29

申请人： Myron Miske ,  Jeffrey B. Davis

发明人： Myron Miske ,  Jeffrey B. Davis

IPC分类号： H03K17/16 ,  H03K17/687

CPC分类号： H03K17/6872 ,  H03K17/162 ,  H03K2217/0018

摘要： A transfer gate or pass gate circuit for transferring logic signals between nodes for a range of available high-potential supply levels. The primary transfer gate is designed to protect against potentials that either exceed either a high-potential or a low-potential level or that undershoot such potential levels. For overshoot (overvoltage) tolerance, this is achieved by coupling a NMOS transistor in parallel with a pair of PMOS transistors that are coupled in series. All three transistors are located between two nodes, either of which can be the input or the output of the transfer gate. The NMOS transistor is designed to be larger than the PMOS transistors and carries most of the transfer capability. The smaller PMOS transistors are designed to eliminate potential drops that would otherwise occur with a single NMOS transistor or with a complementary pair of transistors. For undershoot (undervoltage) tolerance, a PMOS transistor is coupled in parallel with a pair of NMOS transistors that are coupled in series.

摘要翻译： 传输门或通道门电路，用于在可用的高电位电源电平的范围内在节点之间传送逻辑信号。 主转移门被设计为防止超过高电位或低电位电平或潜在水平下降的电位。 对于过冲（过压）公差，可以通过将NMOS晶体管与串联耦合的一对PMOS晶体管并联来实现。 所有三个晶体管位于两个节点之间，其中任一个可以是传输门的输入或输出。 NMOS晶体管被设计为大于PMOS晶体管并且承载大部分传输能力。 较小的PMOS晶体管被设计为消除否则将在单个NMOS晶体管或互补晶体管对发生的电位降。 对于下冲（欠压）公差，PMOS晶体管与串联耦合的一对NMOS晶体管并联耦合。

公开(公告)号：US06768351B1

公开(公告)日：2004-07-27

申请号：US10400978

申请日：2003-03-26

申请人： Jeffrey B. Davis

发明人： Jeffrey B. Davis

IPC分类号： H03B100

CPC分类号： H01L27/0266

摘要： An apparatus and a method for compensating the drain current degradation in pMOS transistors are disclosed. The pMOS transistor receiving drain current compensation is a primary pMOS transistor. The apparatus comprises of a plurality of pMOS transistors subject to drain current degradation correlating to drain current degradation of the primary pMOS transistor, at least one compensation pMOS transistor coupled in parallel with the primary pMOS transistor, and an output voltage decoder to activate one or more of the compensation pMOS transistors to compensate for the drain current degradation of the primary pMOS transistor based on monitored drain current degradation of the plurality of pMOS transistors.

摘要翻译： 公开了用于补偿pMOS晶体管中漏极电流劣化的装置和方法。 接收漏极电流补偿的pMOS晶体管是主要的pMOS晶体管。 该器件包括多个pMOS晶体管，其受到与初级pMOS晶体管的漏极电流劣化相关的漏极电流劣化，至少一个与初级pMOS晶体管并联耦合的补偿pMOS晶体管，以及输出电压解码器，用于激活一个或多个 的补偿pMOS晶体管，以补偿基于多个pMOS晶体管的漏极电流劣化的初级pMOS晶体管的漏极电流劣化。

公开(公告)号：US5418474A

公开(公告)日：1995-05-23

申请号：US126914

申请日：1993-09-24

申请人： Jeffrey B. Davis ,  Jay R. Chapin

发明人： Jeffrey B. Davis ,  Jay R. Chapin

IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03K19/0948 ,  H03K17/16

CPC分类号： H03K19/00361

摘要： A transient-eliminating circuit for minimizing simultaneous conduction through the pullup and pulldown transistors of a buffer circuit. In a buffer circuit used to translate logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail, in which the potentials of the two high-potential rails are not equal, the transient-eliminating circuit is coupled between the output stage and the input stage in such a way that the translator can be utilized independent of power-up sequencing and without any static current I.sub.CCt. The transient-eliminating circuit minimizes simultaneous conduction through the pullup and pulldown transistors of the translator by delaying the turn-on of the pulldown transistor until the pullup transistor is completely off. This is achieved in the preferred embodiment of the invention by coupling an NMOS transistor to the output of the translator circuit to act as an early pulldown on the output by using that NMOS transistor to control a PMOS transistor which is in turn used to control the pulldown transistor. A second NMOS transistor of the transient-eliminating circuit also acts to control the pulldown transistor by operating in the reverse mode of the first NMOS transistor so as to ensure that the NMOS transistor is completely off when required.

摘要翻译： 一种用于最小化通过缓冲电路的上拉和下拉晶体管的同时传导的瞬态消除电路。 在用于将由一个高电位电力轨提供的电路的逻辑信号转换成由两个高电位轨道的电位不相等的另一个高电位电力轨提供的电路的缓冲电路中，瞬态消除电路 以这样的方式耦合在输出级和输入级之间，使得转换器可以独立于上电顺序和没有任何静态电流ICCt而被使用。 瞬态消除电路通过延迟下拉晶体管的导通直到上拉晶体管完全截止来最小化通过转换器的上拉和下拉晶体管的同时导通。 这在本发明的优选实施例中通过将NMOS晶体管耦合到转换器电路的输出来实现，以通过使用该NMOS晶体管来控制PMOS晶体管，以在输出端上作为早期下拉，该PMOS晶体管又用于控制下拉 晶体管。 瞬态消除电路的第二NMOS晶体管还用于通过以第一NMOS晶体管的反向模式操作来控制下拉晶体管，以便确保当需要时NMOS晶体管完全截止。

公开(公告)号：US07475381B2

公开(公告)日：2009-01-06

申请号：US11394621

申请日：2006-03-30

申请人： Jeffrey B. Davis ,  Rajashri Doddamani ,  Byungha Joo ,  Duc G. Nguyen ,  Darshana Surti ,  Eva Yim

发明人： Jeffrey B. Davis ,  Rajashri Doddamani ,  Byungha Joo ,  Duc G. Nguyen ,  Darshana Surti ,  Eva Yim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.

摘要翻译： 标准单元设计中的扩散区跨越单元格边界桥接。 浅沟槽隔离减少，氮化钝化厚度变化减小。

公开(公告)号：USD310849S

公开(公告)日：1990-09-25

申请号：US154185

申请日：1988-02-09

申请人： Jeffrey B. Davis

设计人： Jeffrey B. Davis

公开(公告)号：US06784470B2

公开(公告)日：2004-08-31

申请号：US10383442

申请日：2003-03-06

申请人： Jeffrey B. Davis

发明人： Jeffrey B. Davis

IPC分类号： H01L2972

CPC分类号： H03K19/00384 ,  H01L27/0705 ,  H01L27/098 ,  H03K17/567

摘要： An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

摘要翻译： 集成电路包括可操作以驱动输出节点的输出缓冲器。 输出缓冲器可以包括集成在MOSFET的漏极区域的一部分内的JFET的MOSFET。 JFET可以包括形成在第一导电类型的半导体材料中的与MOSFET的漏极区相邻的第二导电栅极。 电压整形电路可以根据输出节点的电压电平和预定的输出阻抗来控制JFET栅极的偏置。

公开(公告)号：US5381061A

公开(公告)日：1995-01-10

申请号：US24942

申请日：1993-03-02

申请人： Jeffrey B. Davis

发明人： Jeffrey B. Davis

IPC分类号： H03K17/08 ,  H03K17/687 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0948

CPC分类号： H03K19/09429 ,  H03K19/00315 ,  H03K19/01721 ,  H03K2217/0018

摘要： A tristate output buffer circuit provides overvoltage protection from voltage signals on a common bus having a higher voltage level than the internal high potential power rail of the tristate output buffer circuit. A high potential level pseudorail (PV) is coupled to the NWELL of a P channel output pullup transistor (P4). A comparator circuit (P5,P6) couplings the pseudorail (PV) to the output (VOUT). The comparator circuit passgates (P5,P6) are constructed to couple the pseudorail (PV) to the high potential power rail (VCC) for VOUT VCC. A feedback transistor (P1) couples the pseudorail (PV) to an internal node of the tristate output buffer circuit at the control gate node of the output pullup transistor (P4). The feedback transistor (P1) control gate node is coupled to a tristate enable input (EN) for turning on the feedback transistor (P1) during the tristate operating mode and holding off the output pullup transistor (P4). At least one N channel pullup transistor (N1,N2) is coupled between the control gate node of the output pullup transistor (P4) and high potential power rail (VCC) to isolate overvoltage at the internal node from the high potential power rail (VCC). The N channel pullup transistors (N1,N2) are selected to have a turn on voltage threshold VTN less than the absolute value of the turn on voltage threshold VTP of the P channel output pullup transistor.

摘要翻译： 三态输出缓冲电路为具有比三态输出缓冲电路的内部高电位电源电压更高的电压电平的公共总线上的电压信号提供过压保护。 高电位级伪距（PV）耦合到P沟道输出上拉晶体管（P4）的NWELL。 比较电路（P5，P6）将伪线（PV）耦合到输出（VOUT）。 比较器电路通路（P5，P6）被构造为将VOUT VCC的输出（VOUT）。 反馈晶体管（P1）将伪轨迹（PV）耦合到输出上拉晶体管（P4）的控制栅极节点处的三态输出缓冲器电路的内部节点。 反馈晶体管（P1）控制栅极节点耦合到三态使能输入（EN），用于在三态工作模式期间导通反馈晶体管（P1）并保持输出上拉晶体管（P4）。 至少一个N沟道上拉晶体管（N1，N2）被耦合在输出上拉晶体管（P4）的控制栅极节点和高电位电源轨（VCC）之间，以将内部节点处的高电压与高电位电源轨（VCC ）。 N沟道上拉晶体管（N1，N2）被选择为具有小于P沟道输出上拉晶体管的导通电压阈值VTP的绝对值的导通电压阈值VTN。

公开(公告)号：US06879191B2

公开(公告)日：2005-04-12

申请号：US10649261

申请日：2003-08-26

申请人： Jeffrey B. Davis

发明人： Jeffrey B. Davis

IPC分类号： H03K19/003 ,  H03K3/00

CPC分类号： H03K19/00315

摘要： Embodiments of the invention include a data buffer for connecting a core of a data circuit to a data pad. External devices may couple to the data pad even if they have a different power supply voltage than does the core of the data circuit. A pass transistor is coupled between the data pad and a data node in the buffer. A control circuit monitors a signal on the data pad and drives the pass transistor according to the signal received, thereby preventing damage due to voltage mismatch between the data circuit and the external device.

摘要翻译： 本发明的实施例包括用于将数据电路的核心连接到数据焊盘的数据缓冲器。 即使外部设备与数据电路的核心具有不同的电源电压，也可能耦合到数据接口。 传输晶体管耦合在数据焊盘和缓冲器中的数据节点之间。 控制电路监视数据焊盘上的信号，并根据接收到的信号驱动传输晶体管，从而防止数据电路与外部器件之间的电压不匹配造成的损坏。