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7 条记录 (耗时 0.021 秒)

    Measuring bias temperature instability induced ring oscillator frequency degradation
    1.
    发明授权
    Measuring bias temperature instability induced ring oscillator frequency degradation 失效
    测量偏置温度不稳定引起的环形振荡器频率降低

    公开(公告)号：US08587383B2

    公开(公告)日：2013-11-19

    申请号：US13313416

    申请日：2011-12-07

    申请人： David G. Brochu, Jr. ,  Dimitris P. Ioannou ,  Travis S. Merrill ,  Steven W. Mittl

    发明人： David G. Brochu, Jr. ,  Dimitris P. Ioannou ,  Travis S. Merrill ,  Steven W. Mittl

    IPC分类号： G01R23/00 ,  G01R31/3187 ,  H03K3/03

    CPC分类号： G01R31/2824 ,  H03K3/0315

    摘要： A method establishes an initial voltage in a ring oscillator and a logic circuit of an integrated circuit device. Following this, the method enables the operating state of the ring oscillator. After enabling the operating state of the ring oscillator, the method steps up to a stressing voltage in the ring oscillator. The initial voltage is approximately one-half the stressing voltage. The stressing voltage creates operating-level stress within the ring oscillator. The method measures the operating-level frequency within the ring oscillator using an oscilloscope (after stepping up to the stressing voltage).

    摘要翻译： 一种方法在环形振荡器和集成电路器件的逻辑电路中建立初始电压。 此后，该方法启用环形振荡器的工作状态。 在启用环形振荡器的工作状态之后，该方法在环形振荡器中达到应力电压。 初始电压约为应力电压的一半。 应力电压在环形振荡器内产生工作电平应力。 该方法使用示波器测量环形振荡器内的工作电平频率（升压到应力电压之后）。

    MEASURING BIAS TEMPERATURE INSTABILITY INDUCED RING OSCILLATOR FREQUENCY DEGRADATION
    2.
    发明申请
    MEASURING BIAS TEMPERATURE INSTABILITY INDUCED RING OSCILLATOR FREQUENCY DEGRADATION 失效
    测量偏温度不稳定性感应振荡器频率降低

    公开(公告)号：US20130147562A1

    公开(公告)日：2013-06-13

    申请号：US13313416

    申请日：2011-12-07

    申请人： David G. Brochu, JR. ,  Dimitris P. Ioannou ,  Travis S. Merrill ,  Steven W. Mittl

    发明人： David G. Brochu, JR. ,  Dimitris P. Ioannou ,  Travis S. Merrill ,  Steven W. Mittl

    IPC分类号： G01R23/00

    CPC分类号： G01R31/2824 ,  H03K3/0315

    摘要： A method establishes an initial voltage in a ring oscillator and a logic circuit of an integrated circuit device. Following this, the method enables the operating state of the ring oscillator. After enabling the operating state of the ring oscillator, the method steps up to a stressing voltage in the ring oscillator. The initial voltage is approximately one-half the stressing voltage. The stressing voltage creates operating-level stress within the ring oscillator. The method measures the operating-level frequency within the ring oscillator using an oscilloscope (after stepping up to the stressing voltage).

    摘要翻译： 一种方法在环形振荡器和集成电路器件的逻辑电路中建立初始电压。 此后，该方法启用环形振荡器的工作状态。 在启用环形振荡器的工作状态之后，该方法在环形振荡器中达到应力电压。 初始电压约为应力电压的一半。 应力电压在环形振荡器内产生工作电平应力。 该方法使用示波器测量环形振荡器内的工作电平频率（升压到应力电压之后）。

    Dual Stage Voltage Ramp Stress Test for Gate Dielectrics
    3.
    发明申请
    Dual Stage Voltage Ramp Stress Test for Gate Dielectrics 审中-公开
    栅极电介质的双级电压斜坡应力测试

    公开(公告)号：US20120187974A1

    公开(公告)日：2012-07-26

    申请号：US13010081

    申请日：2011-01-20

    申请人： David G. Brochu, JR. ,  Roger A. Dufresne ,  Charles B. LaRow ,  Travis S. Merrill ,  Nilufa Rahim ,  Ernest Y. Wu

    发明人： David G. Brochu, JR. ,  Roger A. Dufresne ,  Charles B. LaRow ,  Travis S. Merrill ,  Nilufa Rahim ,  Ernest Y. Wu

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2623

    摘要： A testing system for testing the integrity of a gate dielectric includes a testing apparatus, the testing apparatus including a test probe configured to contact and provide a voltage across the gate dielectric and to measure a current passing through the gate dielectric. The testing system also includes a computing device coupled to the testing apparatus an causing the testing apparatus to apply a constant voltage as part of a first test to the gate dielectric through the test probe until a first predetermined current is measured passing through the gate dielectric and to apply an increasing voltage to the gate dielectric after the first predetermined current is measured.

    摘要翻译： 用于测试栅极电介质的完整性的测试系统包括测试装置，测试装置包括被配置成接触并提供横跨栅极电介质的电压并测量通过栅极电介质的电流的测试探针。 测试系统还包括耦合到测试装置的计算设备，使得测试设备通过测试探针将恒定电压作为第一测试的一部分施加到栅极电介质，直到通过栅极电介质测量第一预定电流，并且 在测量第一预定电流之后，向栅极电介质施加增加的电压。

    TEST STRUCTURE, METHOD AND CIRCUIT FOR SIMULTANEOUSLY TESTING TIME DEPENDENT DIELECTRIC BREAKDOWN AND ELECTROMIGRATION OR STRESS MIGRATION
    4.
    发明申请
    TEST STRUCTURE, METHOD AND CIRCUIT FOR SIMULTANEOUSLY TESTING TIME DEPENDENT DIELECTRIC BREAKDOWN AND ELECTROMIGRATION OR STRESS MIGRATION 失效
    测试结构，方法和电路同时测试时间依赖电介质断开和电力或应力移动

    公开(公告)号：US20130038334A1

    公开(公告)日：2013-02-14

    申请号：US13207485

    申请日：2011-08-11

    申请人： David G. Brochu, JR. ,  Fen Chen ,  Roger A. Dufresne ,  Travis S. Merrill ,  Michael A. Shinosky

    发明人： David G. Brochu, JR. ,  Fen Chen ,  Roger A. Dufresne ,  Travis S. Merrill ,  Michael A. Shinosky

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2858

    摘要： Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.

    摘要翻译： 用于同时测试电迁移或应力迁移的测试结构在集成电路中的时间依赖介质击穿失效，使用布置为桥接平衡电路的四个测试结构的测试电路和使用测试电路的测试方法。 测试结构的电迁移或应力迁移部分包括通过导电通孔串联连接的导线段的通孔链，形成在集成电路的至少两个相邻布线层中的线段。 测试结构的时间依赖介质击穿部分包括在与数字化的线结构相同的布线级别中与所述线段的少于整个部分相邻的所述至少两个相邻布线层之一中的数字化线结构。

    Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migration
    5.
    发明授权
    Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migration 失效
    测试结构，方法和电路，用于同时测试时间依赖介电击穿和电迁移或应力迁移

    公开(公告)号：US08754655B2

    公开(公告)日：2014-06-17

    申请号：US13207485

    申请日：2011-08-11

    申请人： David G. Brochu, Jr. ,  Fen Chen ,  Roger A. Dufresne ,  Travis S. Merrill ,  Michael A. Shinosky

    发明人： David G. Brochu, Jr. ,  Fen Chen ,  Roger A. Dufresne ,  Travis S. Merrill ,  Michael A. Shinosky

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2858

    摘要： Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.

    摘要翻译： 用于同时测试电迁移或应力迁移的测试结构在集成电路中的时间依赖介质击穿失效，使用布置为桥接平衡电路的四个测试结构的测试电路和使用测试电路的测试方法。 测试结构的电迁移或应力迁移部分包括通过导电通孔串联连接的导线段的通孔链，形成在集成电路的至少两个相邻布线层中的线段。 测试结构的时间依赖介质击穿部分包括在与数字化的线结构相同的布线级别中与所述线段的少于整个部分相邻的所述至少两个相邻布线层之一中的数字化线结构。