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16 条记录 (耗时 0.033 秒)

    Virtualization of pin functionality in a point-to-point interface
    1.
    发明授权
    Virtualization of pin functionality in a point-to-point interface 有权
    在点对点接口中实现引脚功能的虚拟化

    公开(公告)号：US07783809B2

    公开(公告)日：2010-08-24

    申请号：US11173643

    申请日：2005-06-30

    申请人： Keshavan K. Tiruvallur ,  David I. Poisner ,  Herbert H. J. Hum ,  Frank Binns ,  David L. Hill ,  Robert J. Greiner ,  Raymond S. Tetrick

    发明人： Keshavan K. Tiruvallur ,  David I. Poisner ,  Herbert H. J. Hum ,  Frank Binns ,  David L. Hill ,  Robert J. Greiner ,  Raymond S. Tetrick

    IPC分类号： G06F13/24 ,  G06F13/32

    CPC分类号： G06F17/5068 ,  G06F17/5045

    摘要： Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

    摘要翻译： 允许传统引脚功能被替换为“虚拟线”的架构和技术，“虚拟线”可以传达否则将由有线接口传送的信息。 可以在系统控制器和包括虚拟线路值和虚拟换线指示器的处理器之间传递消息。 虚拟线值可以包括对应于已经从物理接口消除的一个或多个引脚的信号，并且虚拟线更改值可以包括虚拟线值是否已经改变的指示。 虚拟线路值和虚拟线路变化指示器的组合可以允许多个物理引脚被消息值替换。

    PROCESSOR SELECTION FOR AN INTERRUPT BASED ON WILLINGNESS TO ACCEPT THE INTERRUPT AND ON PRIORITY
    7.
    发明申请
    PROCESSOR SELECTION FOR AN INTERRUPT BASED ON WILLINGNESS TO ACCEPT THE INTERRUPT AND ON PRIORITY 有权
    基于绝望的中断处理器选择接受中断和优先级

    公开(公告)号：US20090070510A1

    公开(公告)日：2009-03-12

    申请号：US11966356

    申请日：2007-12-28

    申请人： James B. Crossland ,  Shivnandan D. Kaushik ,  Keshavan K. Tiruvallur

    发明人： James B. Crossland ,  Shivnandan D. Kaushik ,  Keshavan K. Tiruvallur

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.

    摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。

    Processor selection for an interrupt based on willingness to accept the interrupt and on priority
    8.
    发明授权
    Processor selection for an interrupt based on willingness to accept the interrupt and on priority 有权
    处理器根据意愿接受中断和优先级中断进行选择

    公开(公告)号：US08032681B2

    公开(公告)日：2011-10-04

    申请号：US11966356

    申请日：2007-12-28

    申请人： James B. Crossland ,  Shivnandan D. Kaushik ,  Keshavan K. Tiruvallur

    发明人： James B. Crossland ,  Shivnandan D. Kaushik ,  Keshavan K. Tiruvallur

    IPC分类号： G06F13/26 ,  G06F13/24 ,  G06F13/32

    CPC分类号： G06F13/24

    摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.

    摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。