公开(公告)号：US07783809B2

公开(公告)日：2010-08-24

申请号：US11173643

申请日：2005-06-30

申请人： Keshavan K. Tiruvallur ,  David I. Poisner ,  Herbert H. J. Hum ,  Frank Binns ,  David L. Hill ,  Robert J. Greiner ,  Raymond S. Tetrick

发明人： Keshavan K. Tiruvallur ,  David I. Poisner ,  Herbert H. J. Hum ,  Frank Binns ,  David L. Hill ,  Robert J. Greiner ,  Raymond S. Tetrick

IPC分类号： G06F13/24 ,  G06F13/32

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

摘要翻译： 允许传统引脚功能被替换为“虚拟线”的架构和技术，“虚拟线”可以传达否则将由有线接口传送的信息。 可以在系统控制器和包括虚拟线路值和虚拟换线指示器的处理器之间传递消息。 虚拟线值可以包括对应于已经从物理接口消除的一个或多个引脚的信号，并且虚拟线更改值可以包括虚拟线值是否已经改变的指示。 虚拟线路值和虚拟线路变化指示器的组合可以允许多个物理引脚被消息值替换。

公开(公告)号：US4807109A

公开(公告)日：1989-02-21

申请号：US6353

申请日：1987-01-14

申请人： Robert L. Farrell ,  Alireza Sarabi ,  Raymond S. Tetrick

发明人： Robert L. Farrell ,  Alireza Sarabi ,  Raymond S. Tetrick

IPC分类号： G06F13/42 ,  G06F13/40

CPC分类号： G06F13/4217

摘要： A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.

摘要翻译： 公开了一种用于耦合多处理器系统内的处理器的高速本地同步总线，使得可以访问本地存储器和辅助处理资源而不影响沿总线的数据业务。 本地总线采用消息控制方法和装置，其包括当处理资源正在响应请求时能够断言WAIT信号的能力。 通过置位WAIT信号，总线上的所有其他操作都将被延迟，直到传输完成。 使用WAIT信号使得能够以与主处理资源不同的速度工作的设备以与主处理资源的时钟速度同步的方式在总线上进行响应。

公开(公告)号：US06622212B1

公开(公告)日：2003-09-16

申请号：US09317442

申请日：1999-05-24

申请人： Raymond S. Tetrick

发明人： Raymond S. Tetrick

IPC分类号： G06F1208

CPC分类号： G06F3/0601 ,  G06F2003/0697

摘要： In an example embodiment, an adaptive method of prefetching data blocks from an input/output device comprises predicting the address of each read operation reading a data block from the input/output device, the prediction based on the address of the immediately preceding read operation from the input/output device; tracking, for each read operation, whether each read operation reads a block data from the same address of the input/output device predicted for the read operation; and prefetching a data block for a read operation from the input/output device in accordance with the state of a state machine, the state of the state machine depending upon whether immediately preceding read operations read a data block from the same address of the input/output device predicted for the read operations.

摘要翻译： 在示例实施例中，从输入/输出设备预取数据块的自适应方法包括：从输入/输出设备预测读取数据块的每个读取操作的地址，基于紧接在前的读取操作的地址进行预测 输入/输出设备; 对于每个读取操作，跟踪每个读取操作是否从为读取操作预测的输入/输出设备的相同地址读取块数据; 并且根据状态机的状态从输入/输出设备预取用于读取操作的数据块，状态机的状态取决于紧接在前的读取操作是否从输入/输出设备的相同地址读取数据块， 输出设备为读取操作预测。

公开(公告)号：US20130339572A1

公开(公告)日：2013-12-19

申请号：US13993695

申请日：2011-12-29

申请人： Blaise Fanning ,  Shekoufeh Qawami ,  Raymond S. Tetrick ,  Frank T. Hady

发明人： Blaise Fanning ,  Shekoufeh Qawami ,  Raymond S. Tetrick ,  Frank T. Hady

IPC分类号： G11C7/10

CPC分类号： G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

摘要： Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

摘要翻译： 公开了用于实现具有直接访问的多级存储器的方法，设备和系统的实施例。 在一个实施例中，该方法包括指定要用作动态随机存取存储器（DRAM）的存储器备选方案的计算机系统中的非易失性随机存取存储器（NVRAM）的量。 该方法通过指定要用作大容量存储设备的存储备用的第二数量的NVRAM来继续。 然后，该方法在计算机系统的操作期间将存储器备选指定中的第一数量的NVRAM的至少第一部分重新指定为存储备选指定。 最后，该方法在计算机系统的操作期间将第二数量的NVRAM的至少第一部分从存储替代指定重新指定到存储器备选指定。

公开(公告)号：US07089399B2

公开(公告)日：2006-08-08

申请号：US10659920

申请日：2003-09-11

申请人： Raymond S. Tetrick

发明人： Raymond S. Tetrick

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F3/0601 ,  G06F2003/0697

摘要： In an example embodiment, an adaptive method of prefetching data blocks from an input/output device comprises predicting the address of each read operation reading a data block from the input/output device, the prediction based on the address of the immediately preceding read operation from the input/output device; tracking, for each read operation, whether each read operation reads a block data from the same address of the input/output device predicted for the read operation; and prefetching a data block for a read operation from the input/output device in accordance with the state of a state machine, the state of the state machine depending upon whether immediately preceding read operations read a data block from the same address of the input/output device predicted for the read operations.

公开(公告)号：US06912556B1

公开(公告)日：2005-06-28

申请号：US09222953

申请日：1998-12-30

申请人： Raymond S. Tetrick

发明人： Raymond S. Tetrick

IPC分类号： G06F7/38 ,  G06F17/18

CPC分类号： G06F17/18

摘要： An averaging measurement circuit comprises a register successively storing a series of data words having a plurality of bits and providing, for each of said data words, a first output consisting of all of the plurality of bits of the data word and a second output consisting of a number of the higher order bits of the data word. A subtracter subtracts each second output of the register from a corresponding data sample and outputs the corresponding subtraction result. An adder adds each first output of the register to a corresponding subtraction result and storing the result in the register.

摘要翻译： 一种平均测量电路包括一个寄存器，它连续地存储一系列具有多个位的数据字，并为每个所述数据字提供由数据字的所有多个位组成的第一输出和由 数据字的高位数的数目。 减法器从对应的数据采样中减去寄存器的每个第二输出，并输出相应的减法结果。 加法器将寄存器的每个第一输出相加到相应的减法结果，并将结果存储在寄存器中。

公开(公告)号：US4570220A

公开(公告)日：1986-02-11

申请号：US555027

申请日：1983-11-25

申请人： Raymond S. Tetrick ,  John Beaston ,  Robert L. Farrell ,  Alireza Sarabi ,  Sudarshan Balachandran ,  Edwin L. Jacks, Jr. ,  Steven D. Kassel

发明人： Raymond S. Tetrick ,  John Beaston ,  Robert L. Farrell ,  Alireza Sarabi ,  Sudarshan Balachandran ,  Edwin L. Jacks, Jr. ,  Steven D. Kassel

IPC分类号： G06F13/374 ,  G06F13/376 ,  G06F13/42 ,  G06F15/16

CPC分类号： G06F13/4243 ,  G06F13/374 ,  G06F13/376 ,  G06F13/4217 ,  G06F13/4239

摘要： A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

摘要翻译： 公开了一种用于在多个数据处理资源之间传送数据的多总线系统架构和改进的数据传输方法。 本发明的总线结构包括将数据处理单元和外围设备（统称为“代理”）互连的并行和串行总线，以允许使用最少的“握手”事件高速地交换数据和消息 在实际数据传输之前。 串行和并行总线原型都由耦合到每个通信代理的消息控制装置控制。 本地总线耦合到系统内的处理代理，使得可以访问本地存储器和二级处理资源而不影响沿着并行总线的数据业务。 由消息控制装置控制对来自其他总线代理的代理的本地总线的资源的直接访问。

公开(公告)号：US09190124B2

公开(公告)日：2015-11-17

申请号：US13993695

申请日：2011-12-29

申请人： Blaise Fanning ,  Shekoufeh Qawami ,  Raymond S. Tetrick ,  Frank T. Hady

发明人： Blaise Fanning ,  Shekoufeh Qawami ,  Raymond S. Tetrick ,  Frank T. Hady

IPC分类号： G06F12/00 ,  G11C7/10 ,  G06F12/02 ,  G06F12/10 ,  G11C16/00 ,  G06F12/08 ,  G11C11/56

CPC分类号： G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

摘要： Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

摘要翻译： 公开了用于实现具有直接访问的多级存储器的方法，设备和系统的实施例。 在一个实施例中，该方法包括指定要用作动态随机存取存储器（DRAM）的存储器备选方案的计算机系统中的非易失性随机存取存储器（NVRAM）的量。 该方法通过指定要用作大容量存储设备的存储备用的第二数量的NVRAM来继续。 然后，该方法在计算机系统的操作期间将存储器备选指定中的第一数量的NVRAM的至少第一部分重新指定为存储备选指定。 最后，该方法在计算机系统的操作期间将第二数量的NVRAM的至少第一部分从存储替代指定重新指定到存储器备选指定。

公开(公告)号：US07360027B2

公开(公告)日：2008-04-15

申请号：US10966231

申请日：2004-10-15

申请人： Ramakrishna Huggahalli ,  Brannon J. Batson ,  Raymond S. Tetrick ,  Robert G. Blankenship

发明人： Ramakrishna Huggahalli ,  Brannon J. Batson ,  Raymond S. Tetrick ,  Robert G. Blankenship

IPC分类号： G06F12/00

CPC分类号： G06F9/383 ,  G06F9/345 ,  G06F12/0862 ,  G06F2212/6028

摘要： An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.

摘要翻译： 提供了一种用于外部代理在计算系统中启动从系统存储器到与目标处理器相关联的高速缓存（其需要数据执行程序）的安排。 外部代理具有数据时，可能会创建并发出预取指令。 预取指令可以与系统互连事务一起发送，或作为单独事务发送到包括系统中的目标处理器的设备。 当接收和识别预取指令时，与目标处理器相关联的硬件预取器可以向系统存储器发出请求以将数据预取到高速缓存。 目标处理器可以比访问系统内存中的数据更有效地访问高速缓存中的数据。 一些预处理也可能与数据预取相关联。

公开(公告)号：US06757798B2

公开(公告)日：2004-06-29

申请号：US09860951

申请日：2001-05-17

申请人： Raymond S. Tetrick

发明人： Raymond S. Tetrick

IPC分类号： G06F1200

CPC分类号： G06F13/161

摘要： An apparatus according to an embodiment of the present invention is disclosed. The apparatus includes a memory interface. The memory interface determines an access time of an original read request. The memory interface outputs a data ready signal when the access time of the original read request expires. An arbiter is coupled to the memory interface. The arbiter arbitrates access to the memory interface. A blocking unit is coupled to the memory interface. The blocking unit blocks a retry of the original read request from reaching the arbiter unit until the data ready signal is output by the memory interface. According to one embodiment of the memory controller a bus interface is coupled to the memory interface. The bus interface issues a deferred read signal to the device making the original read request upon receiving a signal from the arbiter.

摘要翻译： 公开了根据本发明实施例的装置。 该装置包括存储器接口。 存储器接口确定原始读取请求的访问时间。 当原始读取请求的访问时间到期时，存储器接口输出数据就绪信号。 仲裁器耦合到存储器接口。 仲裁者仲裁对存储器接口的访问。 阻塞单元耦合到存储器接口。 阻塞单元阻止原始读取请求的重试到达仲裁器单元，直到数据就绪信号由存储器接口输出。 根据存储器控制器的一个实施例，总线接口耦合到存储器接口。 总线接口向收到来自仲裁器的信号的原始读取请求的器件发出延迟读取信号。