Digital synthesizer
    1.
    发明授权
    Digital synthesizer 失效
    数字合成器

    公开(公告)号:US6078629A

    公开(公告)日:2000-06-20

    申请号:US228140

    申请日:1999-01-11

    摘要: A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single prccessor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

    摘要翻译: 用于与无线用户通信系统中的基站进行无线通信的用户单元包括FIR芯片,DIF(数字中频)芯片,单个处理器芯片和无线电装置。 处理器芯片对数字语音输入信号进行转码以提供数字输入符号; 解调从基站接收的输出信号以提供数字输出符号; 并从数字输出符号合成数字语音输出信号。 FIR芯片FIR对数字输入符号进行滤波,并产生用于对处理器芯片中的代码转换和合成操作进行定时的定时信号。 DIF芯片通过直接数字合成(DDS)数字合成数字中频信号,并用滤波后的输入符号对数字中频信号进行调制,以提供调制中频输入​​信号。 无线电进一步处理调制的输入信号以传输到基站。

    FIR chip for use in a wireless subscriber unit
    5.
    发明授权
    FIR chip for use in a wireless subscriber unit 失效
    FIR芯片用于无线用户单元

    公开(公告)号:US06724851B2

    公开(公告)日:2004-04-20

    申请号:US10412456

    申请日:2003-04-11

    IPC分类号: H04L2300

    摘要: A FIR chip is used in a wireless subscriber unit. The subscriber unit includes a processor for transcoding an input signal to provide digital input symbols. A received output signal is demodulated. Digital output symbols are synthesized from the demodulated output signal processor and filtered digital input symbols are provided. An internal address decoder decodes to allow the processor to access internal functions of the FIR chip. A control and status register allows the processor to read the status of and control the internal functions of the FIR chip. A FIR filter filters the digital input symbols. A transmit timer controls timing which allows the processor to control the FIR filter. A receive timer generates timing signals for timing transcoding operations and synthesizing operations connected to the processor.

    摘要翻译: FIR芯片用于无线用户单元。 用户单元包括用于对输入信号进行代码转换以提供数字输入符号的处理器。 接收到的输出信号被解调。 从解调输出信号处理器合成数字输出符号并提供经过滤波的数字输入符号。 内部地址解码器解码以允许处理器访问FIR芯片的内部功能。 控制和状态寄存器允许处理器读取FIR芯片的内部功能状态并控制其内部功能。 FIR滤波器对数字输入符号进行滤波。 发送定时器控制允许处理器控制FIR滤波器的定时。 接收定时器产生用于定时代码转换操作的定时信号和连接到处理器的合成操作。

    Generating and implementing a signal protocol and interface for higher data rates
    7.
    发明授权
    Generating and implementing a signal protocol and interface for higher data rates 失效
    生成和实现信号协议和接口以实现更高的数据速率

    公开(公告)号:US08700744B2

    公开(公告)日:2014-04-15

    申请号:US12259534

    申请日:2008-10-28

    摘要: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    摘要翻译: 一种数据接口,用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据,以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成,发送和接收形成通信协议的分组的链路控制器使用,并且将数字数据形成为一个或多个类型的数据分组,其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效,低功耗,双向,高速的数据传输机制,可实现微型连接器和薄型柔性电缆,特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    Method, system and computer program for adding a field to a client capability packet sent from a client to a host
    8.
    发明授权
    Method, system and computer program for adding a field to a client capability packet sent from a client to a host 有权
    方法,系统和计算机程序,用于向从客户端发送到主机的客户端能力分组添加一个字段

    公开(公告)号:US08694652B2

    公开(公告)日:2014-04-08

    申请号:US10967007

    申请日:2004-10-15

    IPC分类号: G06F13/00

    摘要: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    摘要翻译: 一种数据接口,用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据,以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成,发送和接收形成通信协议的分组的链路控制器使用,并且将数字数据形成为一个或多个类型的数据分组,其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”型数据链路提供了经济高效,低功耗,双向,高速的数据传输机制,可实现微型连接器和薄型柔性电缆,这些电缆特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    Method, system and computer program for driving a data signal in data interface communication data link
    9.
    发明授权
    Method, system and computer program for driving a data signal in data interface communication data link 有权
    用于在数据接口通信数据链路中驱动数据信号的方法,系统和计算机程序

    公开(公告)号:US08606946B2

    公开(公告)日:2013-12-10

    申请号:US10987123

    申请日:2004-11-12

    IPC分类号: G06F13/00

    摘要: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The data interface includes a system, method and computer program for driving a data signal to a logic one state for a first predetermined range of strobe signals and then driving the data signal to a logic zero state for a second predetermined range of strobe cycles for starting up a digital data interface communication data link from hibernation.

    摘要翻译: 一种数据接口,用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据,以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成,发送和接收形成通信协议的分组的链路控制器使用,并且将数字数据形成为一个或多个类型的数据分组,其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 数据接口包括用于将数据信号驱动到第一预定范围的选通信号的逻辑1状态的系统,方法和计算机程序,然后将数据信号驱动到逻辑0状态以进行第二预定的选通周期范围,以启动 从休眠中提取数字数据接口通信数据链路。

    INTEGRATED CIRCUIT FOR TESTING USING A HIGH-SPEED INPUT/OUTPUT INTERFACE
    10.
    发明申请
    INTEGRATED CIRCUIT FOR TESTING USING A HIGH-SPEED INPUT/OUTPUT INTERFACE 审中-公开
    用于使用高速输入/输出接口进行测试的集成电路

    公开(公告)号:US20120324302A1

    公开(公告)日:2012-12-20

    申请号:US13426235

    申请日:2012-03-21

    IPC分类号: G01R31/3177 G06F11/25

    CPC分类号: G01R31/318572

    摘要: An integrated circuit configured for testing is described. The integrated circuit includes a high-speed input/output interface. The integrated circuit also includes a test controller coupled to the high-speed input/output interface. The integrated circuit further includes test circuitry coupled to the test controller. The test controller controls the test circuitry based on controller protocol test information from the high-speed input/output interface.

    摘要翻译: 描述了配置用于测试的集成电路。 该集成电路包括一个高速输入/输出接口。 集成电路还包括耦合到高速输入/输出接口的测试控制器。 集成电路还包括耦合到测试控制器的测试电路。 测试控制器根据来自高速输入/输出接口的控制器协议测试信息控制测试电路。