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公开(公告)号：US08532098B2
公开(公告)日：2013-09-10
申请号：US12628080
申请日：2009-11-30
申请人： David Reed , Oren Rubinstein , Brad Simeral , Devang Sachdev , Daphne Das , Radha Kanekal , Dennis Ma , Praveen Jain , Manas Mandal
发明人： David Reed , Oren Rubinstein , Brad Simeral , Devang Sachdev , Daphne Das , Radha Kanekal , Dennis Ma , Praveen Jain , Manas Mandal
IPC分类号： H04L12/28
CPC分类号： H04L47/6215 , H04L47/527
摘要： A system and method for communicating over a single virtual channel. The method includes reserving a first group of credits of a credit pool for a first traffic class and a second group of credits of the credit pool for a second traffic class. In addition, a first and second respective groups of tags are reserved from a tag pool for the first and second traffic class. A packet may then be selected from a first buffer for transmission over the virtual channel. The packet may include a traffic indicator of the first traffic class operable to allow the packet to pass a packet of the second traffic class from a second buffer. The method further includes sending the packet over the virtual channel and adjusting the first group of credits and the first group of tags based on having sent a packet of the first traffic class.
摘要翻译： 用于通过单个虚拟通道进行通信的系统和方法。 该方法包括为第一业务类别的信用库的第一组信用和用于第二业务类别的信用库的第二组信用保留。 此外，从用于第一和第二业务等级的标签池保留第一和第二相应的标签组。 然后可以从第一缓冲区中选择分组，以在虚拟信道上进行传输。 分组可以包括第一业务类别的业务指示符，其可操作以允许分组从第二缓冲器传递第二业务类别的分组。 该方法还包括基于已经发送了第一业务类别的分组，通过虚拟信道发送分组并调整第一组信用和第一组标签。
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公开(公告)号：US20110128963A1
公开(公告)日：2011-06-02
申请号：US12628080
申请日：2009-11-30
申请人： David Reed , Oren Rubinstein , Brad Simeral , Devang Sachdev , Daphane Das , Radha Kanekal , Dennis Ma , Praveen Jain , Manas Mandal
发明人： David Reed , Oren Rubinstein , Brad Simeral , Devang Sachdev , Daphane Das , Radha Kanekal , Dennis Ma , Praveen Jain , Manas Mandal
IPC分类号： H04L12/56
CPC分类号： H04L47/6215 , H04L47/527
摘要： A system and method for communicating over a single virtual channel. The method includes reserving a first group of credits of a credit pool for a first traffic class and a second group of credits of the credit pool for a second traffic class. In addition, a first and second respective groups of tags are reserved from a tag pool for the first and second traffic class. A packet may then be selected from a first buffer for transmission over the virtual channel. The packet may include a traffic indicator of the first traffic class operable to allow the packet to pass a packet of the second traffic class from a second buffer. The method further includes sending the packet over the virtual channel and adjusting the first group of credits and the first group of tags based on having sent a packet of the first traffic class.
摘要翻译： 用于通过单个虚拟通道进行通信的系统和方法。 该方法包括为第一业务类别的信用库的第一组信用和用于第二业务类别的信用库的第二组信用保留。 此外，从用于第一和第二业务等级的标签池保留第一和第二相应的标签组。 然后可以从第一缓冲区中选择分组，以在虚拟信道上进行传输。 分组可以包括第一业务类别的业务指示符，其可操作以允许分组从第二缓冲器传递第二业务类别的分组。 该方法还包括基于已经发送了第一业务类别的分组，通过虚拟信道发送分组并调整第一组信用和第一组标签。
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公开(公告)号：US20050237329A1
公开(公告)日：2005-10-27
申请号：US10833694
申请日：2004-04-27
申请人： Oren Rubinstein , David Reed , Jonah Alben
发明人： Oren Rubinstein , David Reed , Jonah Alben
CPC分类号： G09G5/395 , G06F12/0207 , G06F12/0875 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： A graphics processing subsystem uses system memory as its graphics memory for rendering and scanout of images. To prevent deadlock of the data bus, the graphics processing subsystem may use an alternate virtual channel of the data bus to access additional data from system memory needed to complete a write operation of a first data. In communicating with the system memory, a data packet including extended byte enable information allows the graphics processing subsystem to write large quantities of data with arbitrary byte masking to system memory. To leverage the high degree of two-dimensional locality of rendered image data, the graphics processing subsystem arranges image data in a tiled format in system memory. A tile translation unit converts image data virtual addresses to corresponding system memory addresses. The graphics processing subsystem reads image data from system memory and converts it into a display signal.
摘要翻译： 图形处理子系统使用系统存储器作为其图形存储器来渲染和扫描图像。 为了防止数据总线的死锁，图形处理子系统可以使用数据总线的备用虚拟通道来访问从完成第一数据的写入操作所需的系统存储器的附加数据。 在与系统存储器进行通信时，包括扩展字节使能信息的数据包允许图形处理子系统将大量具有任意字节掩蔽的数据写入系统存储器。 为了利用渲染图像数据的高度的二维局部性，图形处理子系统以系统存储器中的平铺格式布置图像数据。 瓦片翻译单元将图像数据虚拟地址转换为相应的系统存储器地址。 图形处理子系统从系统存储器读取图像数据并将其转换为显示信号。
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公开(公告)号：US06535209B1
公开(公告)日：2003-03-18
申请号：US09713447
申请日：2000-11-14
IPC分类号： G06T1700
CPC分类号： G06T15/005
摘要： A computer graphics system splits vertex data into first and second streams and stores the streams in separate regions of memory. In a specific embodiment, the first stream includes positional data and the second stream includes non-positional color and texture data. A visibility subsystem uses only the first stream to perform visibility processing, thus reducing bandwidth requirement. The rendering system processes data from subsets, identified by the visibility subsystem, of both streams required to render the visible part of a scene.
摘要翻译： 计算机图形系统将顶点数据分解为第一和第二流，并将流存储在存储器的单独区域中。 在具体实施例中，第一流包括位置数据，第二流包括非位置颜色和纹理数据。 可见性子系统仅使用第一个流来执行可见性处理，从而减少带宽需求。 渲染系统处理由可见性子系统识别的子集的数据，呈现呈现场景的可见部分所需的两个流。
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公开(公告)号：US07102646B1
公开(公告)日：2006-09-05
申请号：US10888951
申请日：2004-07-09
申请人： Oren Rubinstein , Ming Benjamin Zhu
发明人： Oren Rubinstein , Ming Benjamin Zhu
CPC分类号： G06T15/005 , G06F12/0215 , G06T1/60
摘要： A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.
摘要翻译： 内存系统及其操作方法大大提高了图形系统中内存使用和分配的效率。 在使用平铺架构的图形系统中，不是为每个瓦片预先分配固定量的存储器，本发明根据需求动态地分配每个瓦片的不同量的存储器。 在一个实施例中，可用存储器的全部或一部分被划分成较小的页面，其较好的尺寸相等。 内存分配是通过页面来完成的，这取决于给定图块所需的内存量。
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公开(公告)号：US06856320B1
公开(公告)日：2005-02-15
申请号：US09709964
申请日：2000-11-10
申请人： Oren Rubinstein , Ming Benjamin Zhu
发明人： Oren Rubinstein , Ming Benjamin Zhu
CPC分类号： G06T15/005
摘要： A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.
摘要翻译： 内存系统及其操作方法大大提高了图形系统中内存使用和分配的效率。 在使用平铺架构的图形系统中，不是为每个瓦片预先分配固定量的存储器，本发明根据需求动态地分配每个瓦片的不同量的存储器。 在一个实施例中，可用存储器的全部或一部分被划分成较小的页面，其较好的尺寸相等。 内存分配是通过页面来完成的，这取决于给定图块所需的内存量。
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公开(公告)号：US08762761B2
公开(公告)日：2014-06-24
申请号：US12965154
申请日：2010-12-10
CPC分类号： G06F1/3228 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.
摘要翻译： 根据本技术的实施例的集成电路包括多个引擎，多个引擎级电源门控（ELPG）控制器和用于实现引擎级电源门控仲裁技术的电源门控仲裁器。 电力门控仲裁器可以接收来自一个或多个ELPG控制器的请求以打开其相应的发动机或其中的部分。 电源门控判优器优先处理请求，并向给定的ELPG控制器发送确认，以根据优先级预定顺序打开或关闭其对应的引擎。 给定的ELPG控制器在接收到确认后，打开或关闭其对应的发动机，并向相应的引擎打开或关闭的电源门控仲裁器返回指示。 在从先前服务的ELPG控制器接收到其对应的引擎打开或关闭的指示之后，可以对每个接收到的请求重复该过程。
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公开(公告)号：US07420565B2
公开(公告)日：2008-09-02
申请号：US11249116
申请日：2005-10-11
申请人： Oren Rubinstein , Jonah M. Alben , Wei-Je Huang
发明人： Oren Rubinstein , Jonah M. Alben , Wei-Je Huang
CPC分类号： G06F3/14
摘要： A computer system includes an integrated graphics subsystem and a graphics connector for attaching either an auxiliary graphics subsystem or a loopback card. A first bus connection communicates data from the computer system to the integrated graphics subsystem. With a loopback card in place, data travels from the integrated graphics subsystem back to the computer system via a second bus connection. When the auxiliary graphics subsystem is attached, the integrated graphics subsystem operates in a data forwarding mode. Data is communicated to the integrated graphics subsystem via the first bus connection. The integrated graphics subsystem then forwards data to the auxiliary graphics subsystem. A portion of the second bus connection communicates data from the auxiliary graphics subsystem back to the computer system. The auxiliary graphics subsystem communicates display information back to the integrated graphics subsystem, where it is used to control a display device.
摘要翻译： 计算机系统包括集成图形子系统和用于附加辅助图形子系统或回送卡的图形连接器。 第一总线连接将数据从计算机系统传送到集成图形子系统。 使用回送卡，数据通过第二总线连接从集成图形子系统传回计算机系统。 当附加辅助图形子系统时，集成图形子系统以数据转发模式运行。 数据经由第一总线连接传送到集成图形子系统。 然后，集成图形子系统将数据转发到辅助图形子系统。 第二总线连接的一部分将辅助图形子系统的数据传送回计算机系统。 辅助图形子系统将显示信息传送回集成图形子系统，用于控制显示设备。
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9.发明授权Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width 有权逻辑到物理通道分配，以减少具有可变链路宽度的总线中的时钟功耗公开(公告)号：US07370132B1
公开(公告)日：2008-05-06
申请号：US11281718
申请日：2005-11-16
IPC分类号： G06F13/40
CPC分类号： G06F13/4018 , G09G2330/021 , G09G2350/00 , Y02D10/14 , Y02D10/151
摘要： A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.
摘要翻译： 总线允许响应于总线带宽要求的变化重新协商数据链路的有效串行数据通道的数量。 在一个实施例中，不需要驱动活动数据通道的时钟缓冲器处于非活动状态以减少时钟功率耗散。
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公开(公告)号：US06629188B1
公开(公告)日：2003-09-30
申请号：US09712383
申请日：2000-11-13
IPC分类号： G06F1208
CPC分类号： G06T15/005 , G06F12/0862 , G06F12/0875 , G06T1/60
摘要： A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines, each cache line addressable by a cache line address; a first plurality of storage elements coupled to a first address bus; and a second plurality of storage elements coupled to the first plurality of storage elements. The first plurality of storage elements holds a second number of cache line addresses, and the second plurality of storage elements holds a third number of cache line addresses.
摘要翻译： 一种用于图形和其它系统的高速缓存存储装置。 高速缓冲存储器装置包括具有第一数量的高速缓存行的高速缓存存储器，每个高速缓存行可由高速缓存线地址寻址; 耦合到第一地址总线的第一多个存储元件; 以及耦合到所述第一多个存储元件的第二多个存储元件。 第一多个存储元件保存第二数量的高速缓存线地址，并且第二多个存储元件保存第三数量的高速缓存行地址。
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