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公开(公告)号：US07911277B2
公开(公告)日：2011-03-22
申请号：US12252993
申请日：2008-10-16
IPC分类号： H03F3/191
CPC分类号： H03F3/193 , H03F1/56 , H03F3/45179 , H03F2200/102 , H03F2200/204 , H03F2200/378 , H03F2200/387 , H03F2200/405 , H03F2200/421 , H03F2200/451 , H03F2200/534 , H03F2200/541 , H03F2200/78 , H03F2203/45638
摘要： An adaptively tuned RF power amplifier includes at least one power amplifier stage that has one or more active elements. A tunable output network is coupled to the power amplifier stage and includes one or more adjustable reactive elements. A mismatch detector detects a tuning mismatch based, at least in part, on one or more signals present within the tunable output network, and supplies one or more mismatch signals indicative of a detected tuning mismatch. A tuning controller, responsive to the one or more mismatch signals, controls one or more of the one or more adjustable reactive elements in the tunable output network so as to control the detected mismatch.
摘要翻译： 自适应调谐的RF功率放大器包括至少一个具有一个或多个有源元件的功率放大器级。 可调谐输出网络耦合到功率放大器级并且包括一个或多个可调节的可反应元件。 不匹配检测器至少部分地基于存在于可调谐输出网络内的一个或多个信号来检测调谐失配，并提供指示检测到的调谐失配的一个或多个失配信号。 响应于一个或多个不匹配信号的调谐控制器控制可调输出网络中的一个或多个可调节的可反应元件中的一个或多个，以便控制检测到的失配。
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2.发明授权Bandpass delta sigma truncator and method of truncating a multi-bit digital signal 失效带通三角Σ截断器和截断多位数字信号的方法公开(公告)号：US07145936B2
公开(公告)日：2006-12-05
申请号：US10536946
申请日：2002-12-23
申请人： Ramkishore Ganti , Aria Eshraghi
发明人： Ramkishore Ganti , Aria Eshraghi
CPC分类号： H03M7/3042 , H03M7/3017 , H03M7/3026
摘要： A bandpass delta sigma truncator receives a series of first multi-bit digital signals each having a number of data bits, a first number of sign bits and sign extending means for sign extending each of the first multi-bit digital signals to a second multi-bit digital signal having the same number of data bits as the number of data bits in the first multi-bit digital signals, and a second number of sign bits. The truncator outputs from a series of third multi-bit digital signals a series of fourth multi-bit digital signals each having a selected number of the most significant data bits of the third multi-bit digital signals, and a series of fifth multi-bit digital signals each having the remaining number of the least significant data bits of the third multi-bit digital signals.
摘要翻译： 带通三角形Σ截断器接收一系列具有多个数据位的第一多位数字信号，第一数量的符号位和符号扩展装置，用于将每个第一多位数字信号的符号扩展到第二多位数字信号， 具有与第一多位数字信号中的数据位数相同的数据位数，以及第二数量的符号位。 截断器从一系列第三多位数字信号输出一系列第四多位数字信号，每个第四多位数字信号具有第三多位数字信号的选定数量的最高有效数据位，以及一系列第五多位数字信号 每个数字信号具有第三多位数字信号的剩余数量的最低有效数据位。
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公开(公告)号：US06639946B2
公开(公告)日：2003-10-28
申请号：US09726421
申请日：2000-12-01
申请人： Miaochen Wu , Aria Eshraghi , Theodore Tewksbury
发明人： Miaochen Wu , Aria Eshraghi , Theodore Tewksbury
IPC分类号： H04B1406
摘要： A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.
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公开(公告)号：US07697901B2
公开(公告)日：2010-04-13
申请号：US11394249
申请日：2006-03-30
申请人： Srinath Sridharan , Ahmed Emira , Aria Eshraghi , David Welland
发明人： Srinath Sridharan , Ahmed Emira , Aria Eshraghi , David Welland
CPC分类号： H04B1/0475
摘要： A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.
摘要翻译： 一种方法包括：控制混频器增益，以使用第一控制方案从该混频器提供所选择的功率输出电平的范围，并对该范围的高部分使用第二控制方案。 使用所选择的混频器增益，输入基带信号可以在混频器中上变频到传输频率，并在所选功率输出电平下从混频器输出。
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公开(公告)号：US20090096533A1
公开(公告)日：2009-04-16
申请号：US12252993
申请日：2008-10-16
IPC分类号： H03F1/56
CPC分类号： H03F3/193 , H03F1/56 , H03F3/45179 , H03F2200/102 , H03F2200/204 , H03F2200/378 , H03F2200/387 , H03F2200/405 , H03F2200/421 , H03F2200/451 , H03F2200/534 , H03F2200/541 , H03F2200/78 , H03F2203/45638
摘要： An adaptively tuned RF power amplifier includes at least one power amplifier stage that has one or more active elements. A tunable output network is coupled to the power amplifier stage and includes one or more adjustable reactive elements. A mismatch detector detects a tuning mismatch based, at least in part, on one or more signals present within the tunable output network, and supplies one or more mismatch signals indicative of a detected tuning mismatch. A tuning controller, responsive to the one or more mismatch signals, controls one or more of the one or more adjustable reactive elements in the tunable output network so as to control the detected mismatch.
摘要翻译： 自适应调谐的RF功率放大器包括至少一个具有一个或多个有源元件的功率放大器级。 可调谐输出网络耦合到功率放大器级并且包括一个或多个可调节的可反应元件。 不匹配检测器至少部分地基于存在于可调谐输出网络内的一个或多个信号来检测调谐失配，并且提供表示检测到的调谐失配的一个或多个失配信号。 响应于一个或多个不匹配信号的调谐控制器控制可调输出网络中的一个或多个可调节的可反应元件中的一个或多个，以便控制检测到的失配。
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公开(公告)号：US20070058749A1
公开(公告)日：2007-03-15
申请号：US11227317
申请日：2005-09-14
申请人： Aria Eshraghi , Lysander Lim , Zhongda Wang
发明人： Aria Eshraghi , Lysander Lim , Zhongda Wang
CPC分类号： H03C3/40 , H04L27/2017 , H04L27/367
摘要： A technique includes storing in a memory a set of samples that are distorted so that the samples indicate a distorted representation of a modulation signal. The technique includes in response to the set of samples, generating a second signal that includes a substantially less distorted representation of the modulation signal. The distortion of the samples is used to at least partially compensate for a characteristic that is otherwise imparted to the second signal by the act of generating the second signal.
摘要翻译： 一种技术包括在存储器中存储一组被失真的采样，使得采样指示调制信号的失真表示。 该技术包括响应于该组样本，产生包括调制信号的基本上较不失真的表示的第二信号。 样本的失真被用于至少部分地补偿另外通过产生第二信号的动作赋予第二信号的特性。
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7.发明申请Bandpass delta sigma truncator and method of truncating a multi-bit digital signal 失效带通三角Σ截断器和截断多位数字信号的方法公开(公告)号：US20060120465A1
公开(公告)日：2006-06-08
申请号：US10536946
申请日：2002-12-23
申请人： Ramkishore Ganti , Aria Eshraghi
发明人： Ramkishore Ganti , Aria Eshraghi
IPC分类号： H04B14/06
CPC分类号： H03M7/3042 , H03M7/3017 , H03M7/3026
摘要： A bandpass delta sigma truncator that truncates multi-bit digital input signals to digital output signals (24) having a selected number of the most significant data bits of the digital input signals and a method of truncating multi-bit digital signals. The remaining least significant data bits (3) of the input signals are (a) time delayed (26) by a period of time equal to the time between successive input signals and multiplied by a number (30) related to the ratio of a selected frequency to the frequency of the input signals and the results of the multiplication are added (32) to signs extensions (11) of the input signals, and (b) time delayed by a period of time equal to twice the time between successive input signals and after inversion (28) are added (32) to the sign extensions of the input signals.
摘要翻译： 一种将多位数字输入信号截断为数字输入信号的选定数目的最高有效数据位的数字输出信号（24）的带通三角Σ截断器以及截断多位数字信号的方法。 输入信号的剩余最低有效数据位（3）是（a）时间延迟（26）等于连续输入信号之间的时间的时间段，并乘以与所选择的比例相关的数字（30） 将输入信号的频率和乘法结果的频率相加（32）到输入信号的符号扩展（11），以及（b）时间延迟等于连续输入信号之间的时间的两倍的时间 并将反相（28）加到输入信号的符号扩展上（32）。
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公开(公告)号：US06737849B2
公开(公告)日：2004-05-18
申请号：US10173628
申请日：2002-06-19
申请人： Aria Eshraghi , Xiaodong Wang
发明人： Aria Eshraghi , Xiaodong Wang
IPC分类号： G05F316
CPC分类号： G05F3/30 , Y10S323/907
摘要： A bandgap circuit for producing a constant current having a controllable temperature coefficient. A current mirror supplies first and second substantially identical currents to first and second bipolar transistors. A first resistor is connected across the emitters of the bipolar transistors. A second resistor connects one to the bipolar emitters to a common terminal where the current source currents are recombined and supplied to a common terminal of a power supply. The band gap voltage produced at the common base connections of the bipolar transistors have a voltage temperature coefficient which is controlled by the values of the resistors. A current source is coupled to receive the bandgap voltage and produces a current having a temperature coefficient corresponding to the voltage temperature coefficient of the bandgap voltage.
摘要翻译： 一种用于产生具有可控温度系数的恒定电流的带隙电路。 电流镜向第一和第二双极晶体管提供第一和第二基本相同的电流。 第一电阻器连接在双极晶体管的发射极之间。 第二个电阻将一个与双极发射极连接到公共端，其中电流源电流被重组并提供给电源的公共端。 在双极晶体管的公共基极连接处产生的带隙电压具有由电阻器的值控制的电压温度系数。 耦合电流源以接收带隙电压并产生具有对应于带隙电压的电压温度系数的温度系数的电流。
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公开(公告)号：US06466143B2
公开(公告)日：2002-10-15
申请号：US09824565
申请日：2001-04-03
申请人： Aria Eshraghi , Ramkishore Ganti
发明人： Aria Eshraghi , Ramkishore Ganti
IPC分类号： H03M300
摘要： A digital to analog converter which produces a non-return to zero output voltage. Two SIN DAC converters having return to zero (RZ) output voltages connected to provide a common NRZ output signal. The SIN DAC converters receive the digital signal and a delayed version of the digital signal. The reference sine voltage applied to each SIN DAC have a respective phase shift so that the outputs from each SIN DAC are phase shifted. The combined phase shifted output signals produce an NRZ signal with a reduced susceptibility to clock signal jitter, and which contain significantly less high frequency content than the RZ output signal from a SIN DAC.
摘要翻译： 一个产生不归零输出电压的数模转换器。 两个SIN DAC转换器返回零（RZ）输出电压，以提供公共的NRZ输出信号。 SIN DAC转换器接收数字信号和数字信号的延迟版本。 施加到每个SIN DAC的参考正弦电压具有相应的相移，使得来自每个SIN DAC的输出相移。 组合的相移输出信号产生具有对时钟信号抖动的敏感性降低的NRZ信号，并且其包含比来自SIN DAC的RZ输出信号显着更少的高频率内容。
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公开(公告)号：US20080132178A1
公开(公告)日：2008-06-05
申请号：US11901775
申请日：2007-09-19
申请人： Shouri Chatterjee , Aria Eshraghi , John Khoury
发明人： Shouri Chatterjee , Aria Eshraghi , John Khoury
IPC分类号： H04B1/40
CPC分类号： H03J3/20 , H03J1/0008 , H03J2200/10
摘要： Embodiments may be used to control a controllable element that has a nonlinear but monotonic relationship with a control value. In such embodiments, a system may perform control by receiving an error value corresponding to an error of an output signal from the controllable element, and determining the control value within two iterations of a Newton (Secant) algorithm, where the control value enables generation of the output signal within a predetermined tolerance to a nominal value for the control signal.
摘要翻译： 实施例可以用于控制与控制值具有非线性但单调关系的可控元件。 在这样的实施例中，系统可以通过接收对应于来自可控元件的输出信号的误差的误差值来执行控制，并且在牛顿（分割）算法的两次迭代内确定控制值，其中控制值使得能够生成 输出信号在对于控制信号的标称值的预定容差内。
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