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    Method and circuit for dynamically changing the frequency of clock signals
    1.
    发明授权
    Method and circuit for dynamically changing the frequency of clock signals 失效
    用于动态改变时钟信号频率的方法和电路

    公开(公告)号：US08416900B2

    公开(公告)日：2013-04-09

    申请号：US12354305

    申请日：2009-01-15

    申请人： David Wills Milton ,  Jason Edward Rotella

    发明人： David Wills Milton ,  Jason Edward Rotella

    IPC分类号： H04L7/00

    CPC分类号： G06F1/12

    摘要： A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

    摘要翻译： 一种用于动态改变时钟信号频率的方法和电路。 该方法包括：使用以第二频率操作的第二时钟信号来检测以第一频率工作的第一时钟信号的边沿; 使用所述第一时钟信号检测所述第二时钟信号的边沿; 检测第一和第二时钟信号的重合边缘; 以及在检测到所述重合边缘时将所述第二频率改变为与所述第二频率不同的第三频率。

    METHOD AND CIRCUIT FOR DYNAMICALLY CHANGING THE FREQUENCY OF CLOCK SIGNALS
    2.
    发明申请
    METHOD AND CIRCUIT FOR DYNAMICALLY CHANGING THE FREQUENCY OF CLOCK SIGNALS 失效
    用于动态更改时钟信号频率的方法和电路

    公开(公告)号：US20090122936A1

    公开(公告)日：2009-05-14

    申请号：US12354305

    申请日：2009-01-15

    申请人： David Wills Milton ,  Jason Edward Rotella

    发明人： David Wills Milton ,  Jason Edward Rotella

    IPC分类号： H04L7/00 ,  H03M1/00

    CPC分类号： G06F1/12

    摘要： A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

    摘要翻译： 一种用于动态改变时钟信号频率的方法和电路。 该方法包括：使用以第二频率操作的第二时钟信号来检测以第一频率工作的第一时钟信号的边沿; 使用所述第一时钟信号检测所述第二时钟信号的边沿; 检测第一和第二时钟信号的重合边缘; 以及在检测到所述重合边缘时将所述第二频率改变为与所述第二频率不同的第三频率。

    Memory including master and local word lines coupled to memory cells storing access information
    3.
    发明授权
    Memory including master and local word lines coupled to memory cells storing access information 失效
    存储器，包括耦合到存储访问信息的存储单元的主字线和本地字线

    公开(公告)号：US5727180A

    公开(公告)日：1998-03-10

    申请号：US473159

    申请日：1995-06-07

    申请人： Andrew Davis ,  David Wills Milton

    发明人： Andrew Davis ,  David Wills Milton

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G06F12/12 ,  G11C15/04 ,  G06F12/00 ,  G06F13/00 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C15/04 ,  G06F12/0893 ,  G06F12/123 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/least recently used (LRU) cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. The master word lines and local word lines having approximately the same cycle time. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The architecture circuitry efficiently updates the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.

    摘要翻译： 集成的高速缓存架构，具有低功耗，高抗噪声能力，并全面支持集成有效/最近使用（LRU）缓存写入模式。 高速缓存将TAG，索引和LRU信息直接存储在主字线上，并在本地字线上存储行数据。 访问信息在周期早期可用，允许高速缓存禁用不需要的本地字线。 主字线和本地字线具有大致相同的周期时间。 通过在金属层中布置主和本地字线，使得存储的数据基本上使得不受覆盖噪声源的影响，可以在高速缓存上进行高频互连，而不会干扰存储的数据。 架构电路有效地更新所存储的LRU信息，使得支持组合的数据有效/完整的LRU高速缓存更新协议。

    Cache memory including master and local word lines coupled to memory cells
    4.
    发明授权
    Cache memory including master and local word lines coupled to memory cells 失效
    缓存存储器，包括耦合到存储单元的主字线和本地字线

    公开(公告)号：US5640339A

    公开(公告)日：1997-06-17

    申请号：US662890

    申请日：1996-03-11

    申请人： Andrew Davis ,  David Wills Milton

    发明人： Andrew Davis ,  David Wills Milton

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G06F12/12 ,  G11C15/04 ,  G11C7/00 ,  G11C8/00 ,  G06F13/00

    CPC分类号： G11C15/04 ,  G06F12/0893 ,  G06F12/123 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. A first plurality of memory cells coupled to the master word lines stores access information corresponding to a plurality of data words stored in a second plurality a memory cells coupled to a plurality of local word lines. The cache stores tag, index and Least Recently Used (LRU) information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The cache includes circuitry for efficiently updating the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.

    摘要翻译： 集成缓存结构，具有低功耗，高抗噪声能力，并且完全支持集成有效/ LRU缓存写入模式。 耦合到主字线的第一多个存储单元存储对应于存储在耦合到多个本地字线的第二多个存储单元中的多个数据字的访问信息。 高速缓存直接在主字线上存储标签，索引和最近使用的（LRU）信息，并在本地字线上存储行数据。 访问信息在周期早期可用，允许高速缓存禁用不需要的本地字线。 通过在金属层中布置主和本地字线，使得存储的数据基本上使得不受覆盖噪声源的影响，可以在高速缓存上进行高频互连，而不会干扰存储的数据。 高速缓存包括用于有效地更新存储的LRU信息的电路，使得支持组合的数据有效性/完整的LRU高速缓存更新协议。

    System for expanding a window of valid data
    6.
    发明授权
    System for expanding a window of valid data 有权
    扩展有效数据窗口的系统

    公开(公告)号：US07529962B1

    公开(公告)日：2009-05-05

    申请号：US12098038

    申请日：2008-04-04

    申请人： Malede Wondmagegne Berhanu ,  Christopher Douglas Hanudel ,  Mark William Kuemerle ,  David Wills Milton ,  Clarence Rosser Ogilvie ,  Jack Robert Smith

    发明人： Malede Wondmagegne Berhanu ,  Christopher Douglas Hanudel ,  Mark William Kuemerle ,  David Wills Milton ,  Clarence Rosser Ogilvie ,  Jack Robert Smith

    IPC分类号： G06F1/04 ,  H04L7/00

    CPC分类号： H04L7/0338 ,  H04L7/0008

    摘要： In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.

    摘要翻译： 在一个一般实施例中，提供了一种设计结构，其包括具有至少一个缓冲器的第一延迟线，第一延迟线用于移位时钟，第二延迟线具有至少一个缓冲器，第二延迟线用于移位数据， 以及适于识别数据窗口的预定部分的逻辑块。 此外，逻辑块监视沿延迟线的预定部分的时钟信号，以识别数据窗口的预定部分。 一旦识别了数据窗口的预定部分，逻辑块将与预定部分相关联的数据转发到输出引脚，条件是不存在存储元件，并且条件是不存在反馈线。

    Clock generator having a deskewer
    7.
    发明授权
    Clock generator having a deskewer 失效
    时钟发生器具有电锯

    公开(公告)号：US06507230B1

    公开(公告)日：2003-01-14

    申请号：US09595151

    申请日：2000-06-16

    申请人： David Wills Milton

    发明人： David Wills Milton

    IPC分类号： H03H1126

    CPC分类号： H03K5/156 ,  G06F1/10

    摘要： A clock generator having a deskewer is disclosed. The clock generator includes a waveform generator and a deskewer. Clocked by an input clock signal, the waveform generator generates a waveform signal. The deskewer circuit, which is connected to the waveform generator, gates the waveform signal from the waveform generator with the input clock signal to produce an output clock signal such that the output clock signal has less skew with respect to the input clock signal.

    摘要翻译： 公开了一种具有电锯的时钟发生器。 时钟发生器包括波形发生器和电锯。 由输入时钟信号计时，波形发生器产生波形信号。 连接到波形发生器的偏移电路通过输入时钟信号对波形发生器的波形信号进行门控，以产生输出时钟信号，使得输出时钟信号相对于输入时钟信号具有较小的偏移。

    Fully integrated cache architecture
    8.
    发明授权
    Fully integrated cache architecture 失效
    完全集成的缓存架构

    公开(公告)号：US5717648A

    公开(公告)日：1998-02-10

    申请号：US473158

    申请日：1995-06-07

    申请人： Andrew Davis ,  David Wills Milton

    发明人： Andrew Davis ,  David Wills Milton

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G06F12/12 ,  G11C15/04 ,  G11C7/00

    CPC分类号： G11C15/04 ,  G06F12/0893 ,  G06F12/123 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The cache includes circuitry for efficiently updating the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.

    摘要翻译： 集成缓存结构，具有低功耗，高抗噪声能力，并且完全支持集成有效/ LRU缓存写入模式。 高速缓存将TAG，索引和LRU信息直接存储在主字线上，并在本地字线上存储行数据。 访问信息在周期早期可用，允许高速缓存禁用不需要的本地字线。 通过在金属层中布置主和本地字线，使得存储的数据基本上使得不受覆盖噪声源的影响，可以在高速缓存上进行高频互连，而不会干扰存储的数据。 高速缓存包括用于有效地更新存储的LRU信息的电路，使得支持组合的数据有效性/完整的LRU高速缓存更新协议。