CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING

    公开(公告)号:US20220393672A1

    公开(公告)日:2022-12-08

    申请号:US17889892

    申请日:2022-08-17

    IPC分类号: H03K5/13 G06F1/12

    摘要: Embodiments herein relate to a clock interpolation system. The system may be configured to identify, at a change in logical state of a recovered clock signal, a logical state of a first signal when the first signal is delayed by a delay value. The system may be further configured to identify, at a change in logical state of a second signal, a logical state of the clock signal when the clock signal is delayed by the delay value. Based on the two identifications, the delay value and/or a timing of the clock signal may be adjusted. Other embodiments may be described and/or claimed.

    SINGLE CLOCK SOURCE FOR A MULTIPLE DIE PACKAGE

    公开(公告)号:US20190041895A1

    公开(公告)日:2019-02-07

    申请号:US15952169

    申请日:2018-04-12

    摘要: A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source.

    On-die adaptive arrangements for continuous process, voltage and temperature compensation
    10.
    发明授权
    On-die adaptive arrangements for continuous process, voltage and temperature compensation 有权
    连续工艺,电压和温度补偿的片上自适应布置

    公开(公告)号:US06326802B1

    公开(公告)日:2001-12-04

    申请号:US09409387

    申请日:1999-09-30

    IPC分类号: H03K190185

    CPC分类号: H04L25/0278 H03K19/0005

    摘要: An impedance matching arrangement, including an adaptive circuit. The adaptive circuit includes a first adaptive portion allowing impedance matching according to a predetermined first weighting scheme, and a second adaptive portion allowing impedance matching according to a predetermined second weighting scheme which differs from the first weighting scheme. The first adaptive portion is operable substantially during initialization times, and the second adaptive portion is operable substantially outside initialization times. The first adaptive portion may have a binary weighting scheme, and the second adaptive portion may have a linear weighting scheme. Finally, the adaptive 1 circuit is provided as a portion of an integrated circuit (IC) die.

    摘要翻译: 一种阻抗匹配装置,包括自适应电路。 自适应电路包括允许根据预定的第一加权方案进行阻抗匹配的第一自适应部分和允许根据与第一加权方案不同的预定第二加权方案进行阻抗匹配的第二自适应部分。 第一自适应部分基本上在初始化时间期间可操作,并且第二自适应部分可在大部分的初始化时间之外操作。 第一自适应部分可以具有二进制加权方案,并且第二自适应部分可以具有线性加权方案。 最后,自适应1电路被提供为集成电路(IC)芯片的一部分。