公开(公告)号：US20130314995A1

公开(公告)日：2013-11-28

申请号：US13479649

申请日：2012-05-24

申请人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

发明人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C7/1006 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.

摘要翻译： 一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。 非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。 通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。 选择栅极晶体管的电压也可以电容耦合得更高。 衬底电压可以逐步增加和/或作为连续斜坡增加。 在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。 在另一种方法中，外部和内部虚拟存储元件都浮起来。 由于基板中的电荷捕获减少，存储元件的写擦除耐久性增加。

公开(公告)号：US20120243337A1

公开(公告)日：2012-09-27

申请号：US13153964

申请日：2011-06-06

申请人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

发明人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P-区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US08503229B2

公开(公告)日：2013-08-06

申请号：US13153964

申请日：2011-06-06

申请人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

发明人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/94 ,  H01L21/00 ,  H01L21/8238

CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P-区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US20120228691A1

公开(公告)日：2012-09-13

申请号：US13072130

申请日：2011-03-25

申请人： Mohan Dunga ,  Sanghyun Lee ,  Masaaki Higashitani ,  Tuan Pham

发明人： Mohan Dunga ,  Sanghyun Lee ,  Masaaki Higashitani ,  Tuan Pham

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/66825 ,  G11C11/5642 ,  G11C16/0408 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/40114 ,  H01L29/7881

摘要： Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有PN浮动栅极的非易失性存储元件。 浮置栅极可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有N +区域。 在一些实施例中，隧道氧化物附近的P-区域有助于提供良好的数据保留。 在一些实施例中，控制栅极附近的N +区域有助于实现控制栅极和浮置栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 也可以有效地擦除非易失性存储元件。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。