公开(公告)号：US20130314995A1

公开(公告)日：2013-11-28

申请号：US13479649

申请日：2012-05-24

申请人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

发明人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C7/1006 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.

摘要翻译： 一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。 非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。 通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。 选择栅极晶体管的电压也可以电容耦合得更高。 衬底电压可以逐步增加和/或作为连续斜坡增加。 在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。 在另一种方法中，外部和内部虚拟存储元件都浮起来。 由于基板中的电荷捕获减少，存储元件的写擦除耐久性增加。

公开(公告)号：US20130070530A1

公开(公告)日：2013-03-21

申请号：US13622045

申请日：2012-09-18

申请人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

发明人： Jian Chen ,  Sergei Gorobets ,  Steven Sprouse ,  Tien-Chien Kuo ,  Yan Li ,  Seungpil Lee ,  Alex Mak ,  Deepanshu Dutta ,  Masaaki Higashitani

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/063 ,  G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

摘要翻译： 公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

公开(公告)号：US20130163342A1

公开(公告)日：2013-06-27

申请号：US13335524

申请日：2011-12-22

申请人： Deepanshu Dutta

发明人： Deepanshu Dutta

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/3459

摘要： Methods and non-volatile storage systems are provided for using compensation that depends on the temperature at which the memory cells were programmed. Note that the read level compensation may have a component that is not dependent on the memory cells' Tco. That is, the component is not necessarily based on the temperature dependence of the Vth of the memory cells. The compensation may have a component that is dependent on the difference in width of individual Vth distributions of the different states across different temperatures of program verify. This compensation may be used for both verify and read, although a different amount of compensation may be used during read than during verify.

摘要翻译： 提供了方法和非易失性存储系统，用于使用取决于存储器单元被编程的温度的补偿。 请注意，读取电平补偿可能具有不依赖于存储单元“Tco”的组件。 也就是说，组分不一定基于存储器单元的Vth的温度依赖性。 补偿可以具有取决于程序验证的不同温度下不同状态的各个Vth分布的宽度差异的分量。 该补偿可以用于验证和读取，尽管在读取期间可以使用与验证不同的补偿量。

公开(公告)号：US08248850B2

公开(公告)日：2012-08-21

申请号：US12695918

申请日：2010-01-28

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yan Li

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yan Li

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5642

摘要： An error detection and data recovery operation for a non-volatile memory system. Even after a programming operation for a set of storage elements is successfully completed, the data of some storage elements may be corrupted. For example, erased state storage element may be disturbed by programming of other storage elements. To allow recovery of data in such situations, associated data latches can be configured to allow the erased state storage elements to be distinguished from other data states once programming is completed. Furthermore, a single read operation can be performed after programming is completed. Logical operations are performed using results from the read operation, and values in the data latches, to identify erased state storage elements which have strayed to another data state. If the number of errors exceeds a threshold, a full recovery operation is initiated in which read operations are performed for the remaining states.

摘要翻译： 用于非易失性存储器系统的错误检测和数据恢复操作。 即使在一组存储元件的编程操作成功完成之后，一些存储元件的数据也可能被破坏。 例如，擦除状态存储元件可能受到其他存储元件的编程的干扰。 为了允许在这种情况下恢复数据，相关联的数据锁存器可以被配置为允许擦除状态存储元件在编程完成之后与其他数据状态区分开来。 此外，可以在编程完成之后执行单个读取操作。 使用读取操作的结果和数据锁存器中的值执行逻辑运算，以识别已经偏移到另一数据状态的擦除状态存储元件。 如果错误数量超过阈值，则启动完全恢复操作，在其中执行剩余状态的读取操作。

公开(公告)号：US20120081963A1

公开(公告)日：2012-04-05

申请号：US12894889

申请日：2010-09-30

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states.

摘要翻译： 在编程操作中，达到锁定状态的所选择的存储元件在下一个程序验证迭代的程序部分中经历减少的信道增强，以减少对继续被编程的存储元件的耦合效应。 在随后的程序验证迭代中，锁定的存储元件进行全通道升压。 或者，在锁定之后，可以通过多次程序验证迭代来加强升压。 可以通过调整通道预充电操作的定时和通过加压施加到未选字线的通过电压来设置通道升压量。 对于一个或多个目标数据状态，减少的信道增强可以针对最可能首先达到锁定条件的一系列程序验证迭代来实现。

公开(公告)号：US08081514B2

公开(公告)日：2011-12-20

申请号：US12547449

申请日：2009-08-25

申请人： Man Mui ,  Yingda Dong ,  Binh Lee ,  Deepanshu Dutta

发明人： Man Mui ,  Yingda Dong ,  Binh Lee ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.

摘要翻译： 非易失性存储器系统实现了部分速度和全速编程。 在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线 是固定的 在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。 在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

公开(公告)号：US07800956B2

公开(公告)日：2010-09-21

申请号：US12163073

申请日：2008-06-27

申请人： Dana Lee ,  Deepanshu Dutta ,  Yingda Dong

发明人： Dana Lee ,  Deepanshu Dutta ,  Yingda Dong

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.

摘要翻译： 在多遍编程过程中，非易失性存储器中的编程时间会减少。 在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。 一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。 此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。 在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。 与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

公开(公告)号：US08611148B2

公开(公告)日：2013-12-17

申请号：US13428305

申请日：2012-03-23

申请人： Deepanshu Dutta ,  Jeffrey W Lutze ,  Grishma Shah

发明人： Deepanshu Dutta ,  Jeffrey W Lutze ,  Grishma Shah

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.

公开(公告)号：US20130301351A1

公开(公告)日：2013-11-14

申请号：US13467289

申请日：2012-05-09

申请人： Deepanshu Dutta ,  Shinji Sato ,  Fumiko Yano

发明人： Deepanshu Dutta ,  Shinji Sato ,  Fumiko Yano

IPC分类号： G11C16/04 ,  G11C16/12

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： In a non-volatile storage system, a programming portion of a program-verify iteration has multiple programming pulses, and storage elements along a word line are selected for programming according to a pattern. Unselected storage elements are grouped to benefit from channel-to-channel capacitive coupling from both primary and secondary neighbor storage elements. The coupling is helpful to boost channel regions of the unselected storage elements to a higher channel potential to prevent program disturb. Each selected storage element has a different relative position within its set. For example, during a first programming pulse, first, second and third storage elements are selected in first, second and third sets, respectively. During a second programming pulse, second, third and first storage elements are selected in the first, second and third sets, respectively. During a third programming pulse, third, first and second storage elements are selected in the first, second and third sets, respectively.

摘要翻译： 在非易失性存储系统中，程序验证迭代的编程部分具有多个编程脉冲，并且根据模式选择沿字线的存储元件进行编程。 未选择的存储元件被分组以从主要和次要邻居存储元件的通道到通道的电容耦合受益。 耦合有助于将未选择的存储元件的通道区域升高到更高的通道电位，以防止程序干扰。 每个选定的存储元件在其集合内具有不同的相对位置。 例如，在第一编程脉冲期间，分别在第一，第二和第三组中选择第一，第二和第三存储元件。 在第二编程脉冲期间，分别在第一，第二和第三组中选择第二，第三和第一存储元件。 在第三编程脉冲期间，分别在第一，第二和第三组中选择第三，第一和第二存储元件。

公开(公告)号：US20130250690A1

公开(公告)日：2013-09-26

申请号：US13430502

申请日：2012-03-26

申请人： Chun-Hung Lai ,  Deepanshu Dutta ,  Shinji Sato ,  Gerrit Jan Hemink

发明人： Chun-Hung Lai ,  Deepanshu Dutta ,  Shinji Sato ,  Gerrit Jan Hemink

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10

摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.

摘要翻译： 公开了用于操作非易失性存储器的方法和装置。 一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。 施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。 这可以是源极侧或漏极侧选择晶体管。 这可能会阻止或减少由于DIBL而导致的程序干扰。 这也可以防止或减少由于GIDL可能导致的程序干扰。 当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。 在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。