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公开(公告)号：US20080157270A1
公开(公告)日：2008-07-03
申请号：US11618757
申请日：2006-12-30
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of the invention generally relate to fuse and anti-fuse structures and include a copper conductor positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that an antifuse element region of the dielectric is positioned between the resistor and the metal cap. The antifuse element region of the dielectric is adapted to change resistance values by application of a voltage difference between the resistor and the copper conductor/metal cap. The antifuse element region has a first higher resistance (more closely matching an insulator) before application of the voltage and a second lower resistance (more closely matching a conductor) after application of such voltage. In one embodiment herein the voltage can be supplemented by heating through application of voltage through the first conductor which helps change the resistance of the antifuse element region.
摘要翻译： 本发明的实施例一般涉及熔丝和反熔丝结构，并且包括定位在基板内的铜导体和第一导体上的金属盖。 低k电介质位于基板和金属盖上。 电介质上的氮化钽电阻器，电阻器位于金属帽的上方，使得电介质的反熔丝元件区域位于电阻器和金属帽之间。 电介质的反熔丝元件区域适于通过施加电阻器和铜导体/金属帽之间的电压差来改变电阻值。 在施加电压之后，反熔丝元件区域具有第一高电阻（更紧密地匹配绝缘体）和施加电压之后的第二较低电阻（更接近地匹配导体）。 在本文的一个实施例中，可以通过施加通过第一导体的电压进行加热来补充电压，这有助于改变反熔丝元件区域的电阻。
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公开(公告)号：US20080157268A1
公开(公告)日：2008-07-03
申请号：US11618749
申请日：2006-12-30
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable structure such as a write once read many (WORM) or one time programmable read only memories (OTPROM) is disclosed herein. The structure includes a first conductor (such as copper) positioned within a substrate and a metal cap on the first conductor. A low-k dielectric is on the substrate and the metal cap. A tantalum nitride resistor is on the dielectric, and the resistor is positioned above the metal cap such that a programmable region of the dielectric is positioned between the resistor and the metal cap. The first conductor (including the metal cap), the programmable region of the dielectric, and the resistor form a metal-insulator-metal capacitor. Further, the programmable region of the dielectric is adapted to be permanently changed from heat produced by the resistor when a voltage difference is applied to the first and second ends of the resistor, respectively, through the first and second contacts. Thus, the capacitor comprises a first capacitance before the programmable region is permanently changed by the heat from the resistor and comprises a second capacitance after the programmable region is permanently changed by the heat from the resistor.
摘要翻译： 这里公开了诸如一次写入一次读取（WORM）或一次可编程只读存储器（OTPROM）的可编程结构。 该结构包括位于基板内的第一导体（例如铜）和第一导体上的金属盖。 低k电介质位于基板和金属盖上。 电介质上有一个氮化钽电阻器，电阻器位于金属帽的上方，使电介质的可编程区域位于电阻器和金属帽之间。 第一导体（包括金属盖），电介质的可编程区域和电阻器形成金属 - 绝缘体 - 金属电容器。 此外，电介质的可编程区域分别适用于当通过第一和第二触点将电压差分别施加到电阻器的第一和第二端时由电阻器产生的热量永久地改变。 因此，电容器包括在可编程区域被来自电阻器的热量永久地变化之前的第一电容，并且在可编程区域被来自电阻器的热量永久地改变之后包括第二电容。
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公开(公告)号：US07566593B2
公开(公告)日：2009-07-28
申请号：US11538170
申请日：2006-10-03
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译： 熔丝结构包括插入在基板和熔丝材料层之间的空腔。 空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。 当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。 空隙由支撑熔丝材料层的一对牺牲层基座分开。 通过使用封装介电层将空隙封装以形成空腔。 或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。
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公开(公告)号：US07683416B2
公开(公告)日：2010-03-23
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译： 在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。 电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。 板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。 可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行 结构。
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公开(公告)号：US20080173918A1
公开(公告)日：2008-07-24
申请号：US11935698
申请日：2007-11-06
申请人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-kee Kim , Xi Li
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L28/91 , H01L29/66181
摘要： A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译： 在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成用于去耦应用的适当大值的电容器的设计结构。 电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。 板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。 可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行 结构。
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公开(公告)号：US20080079113A1
公开(公告)日：2008-04-03
申请号：US11538170
申请日：2006-10-03
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译： 熔丝结构包括插入在基板和熔丝材料层之间的空腔。 空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。 当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。 空隙由支撑熔丝材料层的一对牺牲层基座分开。 通过使用封装介电层将空隙封装以形成空腔。 或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。
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公开(公告)号：US07714326B2
公开(公告)日：2010-05-11
申请号：US11683075
申请日：2007-03-07
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.
摘要翻译： 本发明提供了利用电迁移进行编程的反熔丝的结构。 通过在没有导电材料的情况下提供具有高电阻的一部分反熔丝连接，然后通过将导电材料电迁移到反熔丝连接中，反熔丝结构的电阻改变。 通过在反熔丝链路上设置端子，检测和感测反熔丝连接的电特性的变化。 还公开了具有内置感测装置的集成反熔丝和可共享编程晶体管和感测电路的集成反熔丝的二维阵列。
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公开(公告)号：US07723820B2
公开(公告)日：2010-05-25
申请号：US11616965
申请日：2006-12-28
申请人： Deok-kee Kim , Byeongju Park , John M. Safran
发明人： Deok-kee Kim , Byeongju Park , John M. Safran
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , G11C17/16 , G11C17/18 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.
摘要翻译： 本发明提供了一种集成反熔丝的结构，该结构集成了具有集成加热器的集成感测晶体管。 连接到上板的两个端子允许上板的加热，加速在更低偏压下的反熔丝电介质的击穿。 上板的一部分也用作集成感测晶体管的栅极。 反熔丝电介质用作集成晶体管的栅极电介质。 下板包括晶体管的沟道，漏极和源极。 虽然完整，集成感测晶体管允许晶体管电流通过漏极。 当编程时，作为集成晶体管的栅极的反熔丝电介质受到栅极击穿，使栅极短路到沟道并导致漏极电流降低。 集成的反熔丝结构也可以以阵列布线，以提供紧凑的OTP存储器阵列。
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9.发明授权公开(公告)号：US07432755B1
公开(公告)日：2008-10-07
申请号：US11949426
申请日：2007-12-03
申请人： Byeongju Park , Deok-kee Kim , John Matthew Safran , Yongsang Cho
发明人： Byeongju Park , Deok-kee Kim , John Matthew Safran , Yongsang Cho
CPC分类号： G11C17/18
摘要： An electrical fuse programming circuit and a method for programming an electrical fuse within the electrical fuse programming circuit use a programming circuit bus to which are electrically connected in parallel the electrical fuse and a bypass resistor. A current within the programming circuit bus is made to flow through the bypass resistor for a period of time sufficient to stabilize the current, and then sequentially and instantaneously switched to program the electrical fuse.
摘要翻译： 电熔丝编程电路和用于编程电熔丝编程电路内的电熔丝的方法使用编程电路总线并联电连接到熔丝和旁路电阻器。 使编程电路总线内的电流流过旁路电阻一段足以稳定电流的时间，然后顺序并瞬时切换以编程电熔丝。
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公开(公告)号：US20080217658A1
公开(公告)日：2008-09-11
申请号：US11683075
申请日：2007-03-07
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.
摘要翻译： 本发明提供了利用电迁移进行编程的反熔丝的结构。 通过在没有导电材料的情况下提供具有高电阻的一部分反熔丝连接，然后通过将导电材料电迁移到反熔丝连接中，反熔丝结构的电阻改变。 通过在反熔丝链路上设置端子，检测和感测反熔丝连接的电特性的变化。 还公开了具有内置感测装置的集成反熔丝和可共享编程晶体管和感测电路的集成反熔丝的二维阵列。
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