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    Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance
    1.
    发明授权
    Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance 有权
    形成具有低接触电阻的硅化源极/漏极触点的场效应晶体管的方法

    公开(公告)号：US07863201B2

    公开(公告)日：2011-01-04

    申请号：US12402816

    申请日：2009-03-12

    申请人： Yong-Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    发明人： Yong-Kuk Jeong ,  Bong-Seok Suh ,  Dong-Hee Yu ,  Oh-Jung Kwon ,  Seong-Dong Kim ,  O Sung Kwon

    IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/00

    CPC分类号： H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833

    摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

    摘要翻译： 根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。 在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。 通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。 这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。 该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。

    Method of forming a carbon nano-material layer using a cyclic deposition technique
    2.
    发明授权
    Method of forming a carbon nano-material layer using a cyclic deposition technique 有权
    使用循环沉积技术形成碳纳米材料层的方法

    公开(公告)号：US07833580B2

    公开(公告)日：2010-11-16

    申请号：US10859166

    申请日：2004-06-03

    申请人： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

    发明人： Seok-Jun Won ,  Dae-Jin Kwon ,  Yong-Kuk Jeong

    IPC分类号： C23C18/00 ,  C23C16/26

    CPC分类号： C23C16/4554 ,  C23C16/0281 ,  C23C16/26 ,  C30B29/02 ,  C30B29/605

    摘要： A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.

    摘要翻译： 形成碳纳米材料层的方法可以包括循环沉积技术。 在该方法中，可以在基板上形成化学吸附层或化学气相沉积层。 杂质可以从化学吸附层或化学气相沉积层去除，以在基底上形成碳原子层。 可以通过重复该方法形成多于一个的碳原子层。

    Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same
    3.
    发明授权
    Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same 有权
    在互连层之间具有垂直延伸的金属 - 绝缘体 - 金属电容器的逻辑器件及其制造方法

    公开(公告)号：US07476922B2

    公开(公告)日：2009-01-13

    申请号：US10969098

    申请日：2004-10-20

    申请人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

    发明人： Seok-Jun Won ,  Yong-Kuk Jeong ,  Dae-Jin Kwon ,  Min-Woo Song ,  Weon-Hong Kim

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L28/91 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/0805

    摘要： A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

    摘要翻译： 在互连层之间具有垂直延伸的MIM电容器的逻辑器件包括半导体衬底。 下部互连层位于半导体衬底上方，并且上互连层位于下互连层上。 U形下金属板插入在下互连层和上互连层之间。 U形下金属板直接接触下互连层。 电容器电介质层覆盖下金属板的内表面。 此外，电容器介电层具有插入在下金属板的边缘和上互连层之间的延伸部分。 上金属板覆盖电容器介电层的内表面。 上金属板与上互连层接触并被电容器电介质层约束。

    Analog capacitor
    4.
    发明授权
    Analog capacitor 有权
    模拟电容

    公开(公告)号：US07868421B2

    公开(公告)日：2011-01-11

    申请号：US12153306

    申请日：2008-05-16

    申请人： Seok-Jun Won ,  Yong-Kuk Jeong

    发明人： Seok-Jun Won ,  Yong-Kuk Jeong

    IPC分类号： H01L29/92

    CPC分类号： H01L28/60

    摘要： Analog capacitors, and methods of fabricating the same, include a lower electrode having a lower conductive layer, a capacitor dielectric layer on the lower conductive layer, and an upper electrode on the capacitor dielectric layer to be opposite to the lower electrode, wherein the upper electrode includes at least an upper conductive layer in contact with the capacitor dielectric layer, wherein the upper conductive layer has a resistivity higher than that of the lower conductive layer.

    摘要翻译： 模拟电容器及其制造方法包括具有下导电层的下电极，下导电层上的电容器电介质层和电容器电介质层上的与下电极相对的上电极，其中上电极 电极包括至少与电容器介电层接触的上导电层，其中上导电层的电阻率高于下导电层的电阻率。

    Semiconductor device and methods of fabricating the same
    5.
    发明申请
    Semiconductor device and methods of fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US20070158704A1

    公开(公告)日：2007-07-12

    申请号：US11525024

    申请日：2006-09-22

    申请人： Ki-Chul Kim ,  Dong-Suk Shin ,  Yong-Kuk Jeong

    发明人： Ki-Chul Kim ,  Dong-Suk Shin ,  Yong-Kuk Jeong

    IPC分类号： H01L29/76 ,  H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823864

    摘要： A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.

    摘要翻译： 提供了具有蚀刻停止层的半导体器件及其制造方法。 半导体器件可以包括形成在衬底上的衬底和第一栅电极。 可以在第一栅电极的侧壁上形成辅助间隔物。 可以在具有辅助间隔物的衬底上形成蚀刻停止层。 蚀刻停止层和辅助间隔物可以由具有相同应力特性的材料形成。

    Semiconductor devices including trench isolation structures and methods of forming the same
    6.
    发明申请
    Semiconductor devices including trench isolation structures and methods of forming the same 审中-公开
    包括沟槽隔离结构的半导体器件及其形成方法

    公开(公告)号：US20070059898A1

    公开(公告)日：2007-03-15

    申请号：US11393546

    申请日：2006-03-30

    申请人： Dong-Suk Shin ,  Seung-Jin Lee ,  Yong-Kuk Jeong ,  Ki-Kwan Park

    发明人： Dong-Suk Shin ,  Seung-Jin Lee ,  Yong-Kuk Jeong ,  Ki-Kwan Park

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L21/76232

    摘要： Trench isolation methods include forming a first trench and a second trench, having a larger width than the first trench, in a semiconductor substrate. A lower isolation layer is formed having a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall of the second trench using a first high density plasma deposition process, the second thickness being greater than the first thickness. An upper isolation layer is formed on the semiconductor substrate including the lower isolation layer using a second high density plasma deposition process, different from the first high density plasma deposition process. The first and second high density plasma deposition processes may be chemical vapor deposition processes. Semiconductor devices including a trench isolation structure are also provided.

    摘要翻译： 沟槽隔离方法包括在半导体衬底中形成具有比第一沟槽更大的宽度的第一沟槽和第二沟槽。 使用第一高密度等离子体沉积工艺在第一沟槽的上侧壁上形成具有第一厚度的第一厚度和在第二沟槽的上侧壁上的第二厚度的下隔离层，第二厚度大于第一厚度。 使用不同于第一高密度等离子体沉积工艺的第二高密度等离子体沉积工艺在包括下隔离层的半导体衬底上形成上隔离层。 第一和第二高密度等离子体沉积工艺可以是化学气相沉积工艺。 还提供了包括沟槽隔离结构的半导体器件。

    Capacitor of semiconductor device and method for manufacturing the same
    10.
    发明申请
    Capacitor of semiconductor device and method for manufacturing the same 审中-公开
    半导体器件的电容器及其制造方法

    公开(公告)号：US20060124987A1

    公开(公告)日：2006-06-15

    申请号：US11345776

    申请日：2006-02-01

    申请人： Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

    发明人： Seok-Jun Won ,  Myong-geun Yoon ,  Yong-Kuk Jeong ,  Dae-jin Kwon

    IPC分类号： H01L29/94

    CPC分类号： H01L21/022 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/56 ,  H01L28/65

    摘要： Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.

    摘要翻译： 提供一种半导体器件的电容器。 电容器包括设置在半导体衬底上的电容器下电极。 包含氧化铝（Al 2 O 3 3）的第一电介质层设置在电容器下电极上。 包括具有比氧化铝介电常数更高的介电常数的材料的第二电介质层设置在第一电介质层上。 包含氧化铝的第三电介质层设置在第二电介质层上。 电容器上电极设置在第三电介质层上。 本发明的电容器可以改善电气性能。 因此，可以降低功耗，并且每单位面积的电容足够高以实现高集成度。