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1.发明授权Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same 有权互连集成金属 - 绝缘体 - 金属电容器及其制造方法公开(公告)号：US06342734B1
公开(公告)日：2002-01-29
申请号：US09559934
申请日：2000-04-27
IPC分类号： H01L2348
CPC分类号： H01L28/40 , H01L21/32051 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal capacitor is formed between interconnect layers of an integrated circuit with one of the plates of the capacitor formed integrally with one of the interconnect layers. A dielectric layer is formed on top of the interconnect layer, and a top capacitor plate is formed thereon. A bottom plate is defined by the interconnect layer and extends laterally beyond the top plate so that via interconnects may connect to both plates. An intermetal dielectric (IMD) layer separates the interconnect layer and the capacitor from the next interconnect layer above, and the via interconnects are formed through the IMD layer to connect the above interconnect layer to the capacitor plates. The dielectric layer on top of the interconnect layer that defines the bottom plate and another dielectric layer formed on top of the top plate may serve as etch stops for forming the vias for the via interconnects to different levels.
摘要翻译： 在集成电路的互连层之间形成金属 - 绝缘体 - 金属电容器，其中电容器的一个板与一个互连层一体形成。 在互连层的顶部形成有电介质层，在其上形成顶部电容器板。 底板由互连层限定，并且横向延伸超过顶板，使得通孔互连可以连接到两个板。 金属间电介质（IMD）层将互连层和电容器与上面的下一个互连层分离，并且通孔互连通过IMD层形成，以将上述互连层连接到电容器板。 限定底板的互连层顶部的介电层和形成在顶板顶部的另一电介质层可用作形成用于通孔互连的不同级别的通孔的蚀刻停止。
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2.发明授权Electronically controlled optically-active device array for high-speed receiving and transmitting of fiber optic signals 有权用于高速接收和传输光纤信号的电子控制光学有源器件阵列公开(公告)号：US06445479B1
公开(公告)日：2002-09-03
申请号：US09216396
申请日：1998-12-18
IPC分类号： H04B1006
CPC分类号： H04B10/69
摘要： A receiver for detecting a stream of optical data bits which are transmitted at a predetermined frequency includes a plurality of optically-active devices arranged on an integrated circuit substrate in an array. The plurality of optically-active devices are capable of being positioned to receive the stream of optical data bits which are transmitted as light, and each of the optically active devices is capable of detecting light in an optically active state and generating a detected signal corresponding thereto. A control circuit receives a clock signal at a rate corresponding to the predetermined frequency and generates control signals which cause a different one of the plurality of optically-active devices to be in the optically active state during each successive period and thereby detect the presence of light during each of said successive periods and generate the detected signals corresponding to the data bit stream.
摘要翻译： 用于检测以预定频率发送的光数据比特流的接收机包括布置在阵列中的集成电路基板上的多个光学有源装置。 多个光学活动装置能够被定位成接收作为光传输的光数据比特流，并且每个光学有源装置能够检测光学活动状态的光并产生与其对应的检测信号 。 控制电路以对应于预定频率的速率接收时钟信号，并且产生控制信号，这些控制信号使得多个光学有源器件中的不同的一个在每个连续的周期期间处于光学活动状态，从而检测光的存在 并且产生与数据比特流对应的检测信号。
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公开(公告)号：US06177305B1
公开(公告)日：2001-01-23
申请号：US09213847
申请日：1998-12-17
IPC分类号： H01L21285
CPC分类号： H01L28/40 , H01L21/28556 , H01L21/28568 , H01L21/31604 , H01L28/56 , Y10S438/907
摘要： Techniques for fabricating metal-insulator-metal (MIM) capacitive structures by chemical vapor deposition (CVD) help avoid the formation of a porous metal oxide film at the interface between the lower electrode and the insulating layer. One method of fabricating an integrated circuit includes depositing a first titanium nitride electrode layer on a wafer by CVD and subsequently depositing an insulating layer on the first electrode. The insulating layer can comprise a material selected from the group consisting of titanium oxide (TiOx), titanium oxynitride (TiOxNy), titanium oxycarbonitride (TiOxNyCz) and silicon oxide (SiOx), and is deposited by CVD without exposing the first titanium nitride electrode to atmosphere. A second titanium nitride electrode layer also is deposited on the insulating layer by CVD. The various layers of the capacitive structure, including the insulating layer, can be deposited in situ in a single CVD chamber.
摘要翻译： 通过化学气相沉积（CVD）制造金属 - 绝缘体 - 金属（MIM）电容结构的技术有助于避免在下电极和绝缘层之间的界面处形成多孔金属氧化物膜。 制造集成电路的一种方法包括通过CVD沉积在晶片上的第一氮化钛电极层，并随后在第一电极上沉积绝缘层。 绝缘层可以包括选自氧化钛（TiO x），氮氧化钛（TiO x N y），碳氮氧化钛（TiO x N y C z）和氧化硅（SiO x）的材料，并且通过CVD沉积而不暴露第一氮化钛电极 大气层。 第二氮化钛电极层也通过CVD沉积在绝缘层上。 包括绝缘层的电容结构的各个层可以在单个CVD室中原位沉积。
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4.发明授权Method for tungsten nucleation from WF.sub.6 using titanium as a reducing agent 失效使用钛作为还原剂的WF6钨成核方法
公开(公告)号：US5963828A
公开(公告)日：1999-10-05
申请号：US773471
申请日：1996-12-23
IPC分类号： C23C16/02 , H01L21/3205 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76879 , C23C16/0281 , H01L21/32055
摘要： A method in a semiconductor process for forming a layer of a selected compound on a substrate of a semiconductor device. A layer of titanium is formed on the substrate as a sacrificial layer. The layer of titanium is reduced using a gaseous form of a fluorine containing compound in which the fluorine containing compound includes the selected compound that is to be formed on the substrate of the semiconductor device.
摘要翻译： 一种用于在半导体器件的衬底上形成选定化合物层的半导体工艺中的方法。 在衬底上形成钛层作为牺牲层。 使用气体形式的含氟化合物还原钛层，其中含氟化合物包括将在半导体器件的衬底上形成的选定化合物。
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5.发明授权Isolated metal plug process for use in fabricating carbon nanotube memory cells 失效用于制造碳纳米管记忆单元的隔离金属塞工艺公开(公告)号：US07884430B2
公开(公告)日：2011-02-08
申请号：US12710477
申请日：2010-02-23
IPC分类号： H01L29/84
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译： 本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。 这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。 第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。 纳米管横杆元件布置成跨越下室。 第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。 屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。 存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。
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6.发明申请ISOLATED METAL PLUG PROCESS FOR USE IN FABRICATING CARBON NANOTUBE MEMORY CELLS 失效用于制备碳纳米管存储器细胞的隔离金属压片方法公开(公告)号：US20100148277A1
公开(公告)日：2010-06-17
申请号：US12710477
申请日：2010-02-23
IPC分类号： H01L27/112
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译： 本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。 这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。 第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。 纳米管横杆元件布置成跨越下室。 第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。 屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。 存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。
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7.发明授权Isolated metal plug process for use in fabricating carbon nanotube memory cells 有权用于制造碳纳米管记忆单元的隔离金属塞工艺公开(公告)号：US07824946B1
公开(公告)日：2010-11-02
申请号：US11429069
申请日：2006-05-05
CPC分类号： H01H1/0094 , Y10S977/724 , Y10S977/732 , Y10S977/943
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
摘要翻译： 本发明涉及制造具有纳米管横杆元件的机电存储器单元的结构和方法。 这种存储单元包括具有与晶体管电接触的接触的晶体管的衬底。 第一支撑层形成在衬底上，其开口限定了电触点上方的下腔室。 纳米管横杆元件布置成跨越下室。 第二支撑层形成有开口，所述开口限定在所述下腔室上方的顶部腔室，所述顶部腔室包括延伸超出所述下部腔室的边缘以暴露所述第一支撑层的顶部表面的一部分的延伸区域。 屋顶层覆盖顶部室的顶部，并且包括露出顶部室的延伸区域的一部分并且包括延伸到顶部层中的孔中以密封顶部和底部室的插塞的孔。 存储单元还包括覆盖在横杆元件上的电极，使得电信号可以激活电极以吸引或排斥交叉开关元件以设置晶体管的存储状态。
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公开(公告)号：US07666701B1
公开(公告)日：2010-02-23
申请号：US11429069
申请日：2006-05-05
摘要： The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.
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9.发明授权Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion beams 有权通过激励氮离子束将氮掺入金属硅酸盐基电介质的方法公开(公告)号：US06864141B1
公开(公告)日：2005-03-08
申请号：US10453118
申请日：2003-06-03
申请人： Wai Lo , James P. Kimball , Verne C. Hornback
发明人： Wai Lo , James P. Kimball , Verne C. Hornback
IPC分类号： H01L21/28 , H01L21/3115 , H01L21/314 , H01L21/8238 , H01L29/51 , H01L21/283 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L21/823857 , H01L29/518
摘要： A method of making a thin gate dielectric includes providing a metal silicate on a silicon substrate. Nitrogen is implanted into the metal silicate.
摘要翻译： 制造薄栅极电介质的方法包括在硅衬底上提供金属硅酸盐。 将氮气注入到金属硅酸盐中。
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10.发明授权Thin gate dielectric for a CMOS transistor and method of fabrication thereof 失效CMOS晶体管的薄栅极电介质及其制造方法公开(公告)号：US06849512B1
公开(公告)日：2005-02-01
申请号：US10283630
申请日：2002-10-30
申请人： Wai Lo , James P. Kimball , Verne C. Hornback
发明人： Wai Lo , James P. Kimball , Verne C. Hornback
IPC分类号： H01L21/265 , H01L21/28 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28211 , H01L21/26506 , H01L21/2822 , H01L21/28238 , H01L29/518
摘要： A method of making a thin gate dielectric includes implanting a barrier substance into a region of a silicon substrate. A capacitance-increasing material is implanted into the silicon substrate. An outside layer of the silicon substrate is oxidized to form a first silicon oxide layer. The silicon substrate is oxidized between the first silicon oxide layer and the region.
摘要翻译： 制造薄栅极电介质的方法包括将阻挡物质注入到硅衬底的区域中。 将电容增加材料注入到硅衬底中。 硅衬底的外层被氧化以形成第一氧化硅层。 硅衬底在第一氧化硅层和区域之间被氧化。
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