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    Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same
    1.
    发明授权
    Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same 有权
    互连集成金属 - 绝缘体 - 金属电容器及其制造方法

    公开(公告)号：US06342734B1

    公开(公告)日：2002-01-29

    申请号：US09559934

    申请日：2000-04-27

    申请人： Derryl D. J. Allman ,  John Q. Walker ,  Verne C. Hornback ,  Todd A. Randazzo

    发明人： Derryl D. J. Allman ,  John Q. Walker ,  Verne C. Hornback ,  Todd A. Randazzo

    IPC分类号： H01L2348

    CPC分类号： H01L28/40 ,  H01L21/32051 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal-insulator-metal capacitor is formed between interconnect layers of an integrated circuit with one of the plates of the capacitor formed integrally with one of the interconnect layers. A dielectric layer is formed on top of the interconnect layer, and a top capacitor plate is formed thereon. A bottom plate is defined by the interconnect layer and extends laterally beyond the top plate so that via interconnects may connect to both plates. An intermetal dielectric (IMD) layer separates the interconnect layer and the capacitor from the next interconnect layer above, and the via interconnects are formed through the IMD layer to connect the above interconnect layer to the capacitor plates. The dielectric layer on top of the interconnect layer that defines the bottom plate and another dielectric layer formed on top of the top plate may serve as etch stops for forming the vias for the via interconnects to different levels.

    摘要翻译： 在集成电路的互连层之间形成金属 - 绝缘体 - 金属电容器，其中电容器的一个板与一个互连层一体形成。 在互连层的顶部形成有电介质层，在其上形成顶部电容器板。 底板由互连层限定，并且横向延伸超过顶板，使得通孔互连可以连接到两个板。 金属间电介质（IMD）层将互连层和电容器与上面的下一个互连层分离，并且通孔互连通过IMD层形成，以将上述互连层连接到电容器板。 限定底板的互连层顶部的介电层和形成在顶板顶部的另一电介质层可用作形成用于通孔互连的不同级别的通孔的蚀刻停止。

    Fabrication of metal-insulator-metal capacitive structures
    2.
    发明授权
    Fabrication of metal-insulator-metal capacitive structures 有权
    金属 - 绝缘体 - 金属电容结构的制造

    公开(公告)号：US06177305B1

    公开(公告)日：2001-01-23

    申请号：US09213847

    申请日：1998-12-17

    申请人： Verne C. Hornback ,  Derryl D. J. Allman ,  Newell E. Chiesl

    发明人： Verne C. Hornback ,  Derryl D. J. Allman ,  Newell E. Chiesl

    IPC分类号： H01L21285

    CPC分类号： H01L28/40 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/31604 ,  H01L28/56 ,  Y10S438/907

    摘要： Techniques for fabricating metal-insulator-metal (MIM) capacitive structures by chemical vapor deposition (CVD) help avoid the formation of a porous metal oxide film at the interface between the lower electrode and the insulating layer. One method of fabricating an integrated circuit includes depositing a first titanium nitride electrode layer on a wafer by CVD and subsequently depositing an insulating layer on the first electrode. The insulating layer can comprise a material selected from the group consisting of titanium oxide (TiOx), titanium oxynitride (TiOxNy), titanium oxycarbonitride (TiOxNyCz) and silicon oxide (SiOx), and is deposited by CVD without exposing the first titanium nitride electrode to atmosphere. A second titanium nitride electrode layer also is deposited on the insulating layer by CVD. The various layers of the capacitive structure, including the insulating layer, can be deposited in situ in a single CVD chamber.

    摘要翻译： 通过化学气相沉积（CVD）制造金属 - 绝缘体 - 金属（MIM）电容结构的技术有助于避免在下电极和绝缘层之间的界面处形成多孔金属氧化物膜。 制造集成电路的一种方法包括通过CVD沉积在晶片上的第一氮化钛电极层，并随后在第一电极上沉积绝缘层。 绝缘层可以包括选自氧化钛（TiO x），氮氧化钛（TiO x N y），碳氮氧化钛（TiO x N y C z）和氧化硅（SiO x）的材料，并且通过CVD沉积而不暴露第一氮化钛电极 大气层。 第二氮化钛电极层也通过CVD沉积在绝缘层上。 包括绝缘层的电容结构的各个层可以在单个CVD室中原位沉积。

    Electronically controlled optically-active device array for high-speed receiving and transmitting of fiber optic signals
    3.
    发明授权
    Electronically controlled optically-active device array for high-speed receiving and transmitting of fiber optic signals 有权
    用于高速接收和传输光纤信号的电子控制光学有源器件阵列

    公开(公告)号：US06445479B1

    公开(公告)日：2002-09-03

    申请号：US09216396

    申请日：1998-12-18

    申请人： Verne C. Hornback ,  Derryl D. J. Allman

    发明人： Verne C. Hornback ,  Derryl D. J. Allman

    IPC分类号： H04B1006

    CPC分类号： H04B10/69

    摘要： A receiver for detecting a stream of optical data bits which are transmitted at a predetermined frequency includes a plurality of optically-active devices arranged on an integrated circuit substrate in an array. The plurality of optically-active devices are capable of being positioned to receive the stream of optical data bits which are transmitted as light, and each of the optically active devices is capable of detecting light in an optically active state and generating a detected signal corresponding thereto. A control circuit receives a clock signal at a rate corresponding to the predetermined frequency and generates control signals which cause a different one of the plurality of optically-active devices to be in the optically active state during each successive period and thereby detect the presence of light during each of said successive periods and generate the detected signals corresponding to the data bit stream.

    摘要翻译： 用于检测以预定频率发送的光数据比特流的接收机包括布置在阵列中的集成电路基板上的多个光学有源装置。 多个光学活动装置能够被定位成接收作为光传输的光数据比特流，并且每个光学有源装置能够检测光学活动状态的光并产生与其对应的检测信号 。 控制电路以对应于预定频率的速率接收时钟信号，并且产生控制信号，这些控制信号使得多个光学有源器件中的不同的一个在每个连续的周期期间处于光学活动状态，从而检测光的存在 并且产生与数据比特流对应的检测信号。

    Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure
    5.
    发明授权
    Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure 有权
    在集成电路结构上形成低k碳掺杂氧化硅介电材料的工艺

    公开(公告)号：US06583026B1

    公开(公告)日：2003-06-24

    申请号：US09872058

    申请日：2001-05-31

    申请人： Derryl D. J. Allman ,  Ponce Saopraseuth ,  Hemanshu D. Bhatt

    发明人： Derryl D. J. Allman ,  Ponce Saopraseuth ,  Hemanshu D. Bhatt

    IPC分类号： H01L2176

    CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/31633

    摘要： A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C. or less of the subsequent deposition temperature used for formation of the film of lkc-dsodm. In another aspect of the invention the pausing step further includes, before deposition of the next layer of lkc-dsodm, flowing a source of non-reactive gas over the surface of the newly deposited layer of lkc-dsodm to facilitate outgassing and removal of byproducts resulting from the preceding formation and deposition of lkc-dsodm.

    摘要翻译： 在集成电路结构上形成低k碳掺杂氧化硅电介质材料（lkc-dsodm）的方法的特征在于集成电路结构的高纵横比区域中的平坦度和良好的间隙填充，以及改进的膜强度 和坚持，更少的副产品被困在电影中。 该方法包括：在反应器中的集成电路结构上沉积多层lkc-dsodm; 并且在沉积每层lkc-dsodm之后并在沉积另外一层lkc-dsodm之前暂停。 该方法还可以包括首先在集成电路结构上形成富硅和富氮介电材料的基底或阻挡层，等离子体蚀刻阻挡层的上表面，以便于随后沉积的lkc-dsodm粘附到 然后在沉积第一层lkc-dsodm之前，将蚀刻的阻挡层冷却到用于形成lkc-dsodm膜的后续沉积温度的10℃以内。 在本发明的另一方面，暂停步骤还包括在沉积下一层lkc-dsodm之前，将非反应性气体源流过新沉积的lkc-dsodm层的表面以便于除气和除去副产物 由于以前的lkc-dsodm的形成和沉积而产生。

    Interconnect-embedded metal-insulator-metal capacitor
    7.
    发明授权
    Interconnect-embedded metal-insulator-metal capacitor 有权
    互连嵌入式金属 - 绝缘体 - 金属电容器

    公开(公告)号：US06504202B1

    公开(公告)日：2003-01-07

    申请号：US09496971

    申请日：2000-02-02

    申请人： Derryl D. J. Allman ,  Kenneth Fuchs

    发明人： Derryl D. J. Allman ,  Kenneth Fuchs

    IPC分类号： H01L2976

    CPC分类号： H01L28/40 ,  H01L21/768 ,  H01L28/75

    摘要： A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

    摘要翻译： 金属 - 绝缘体 - 金属电容器嵌入在集成电路（IC）的互连层中。 互连层具有空腔，并且电容器形成在空腔中，电容器的一个板与互连层的导电层成一体，因此电容器板与互连层电连通。 互连层具有多个导电层，包括在制造IC期间在特定温度下经受变形的诸如铝的层，并且空腔延伸穿过该层。 互连层的剩余导电层限定电容器板中的一个，并且在腔内形成介电层和另一电容器板。 通过大致相同长度的互连电连接到顶板并且通过互连层连接到底板。

    Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
    9.
    发明授权
    Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same 有权
    具有层间对准标记的半导体晶片及其制造方法

    公开(公告)号：US6136662A

    公开(公告)日：2000-10-24

    申请号：US311253

    申请日：1999-05-13

    申请人： Derryl D. J. Allman ,  Curtis C. Hainds ,  Charles W. Jurgensen ,  Brian R. Lee

    发明人： Derryl D. J. Allman ,  Curtis C. Hainds ,  Charles W. Jurgensen ,  Brian R. Lee

    IPC分类号： G03F9/00 ,  H01L23/544 ,  H01L21/76 ,  H01L21/302 ,  H01L21/4763

    CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

    摘要： A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.

    摘要翻译： 在半导体晶片中形成层间对准标记的方法包括在与半导体晶片相关联的衬底上沉积第一导体层的步骤。 该方法还包括在第一导体层中制造多个对准沟槽的步骤。 此外，该方法包括在第一导体层上沉积第一绝缘体层以填充对准沟槽的数量的步骤。 此外，该方法包括以下步骤：从对准沟槽的数量去除与第一绝缘体层相关联的材料，使得第一导体层的上表面和第一绝缘体层的上表面限定第一对准步骤特征，其具有 一个预定的高度。 该方法还包括在去除步骤之后在半导体晶片上沉积第二导体层的步骤。 还公开了半导体晶片。

    Method for forming a bipolar emitter using doped SOG
    10.
    发明授权
    Method for forming a bipolar emitter using doped SOG 失效
    使用掺杂SOG形成双极型发射极的方法

    公开(公告)号：US5322805A

    公开(公告)日：1994-06-21

    申请号：US961973

    申请日：1992-10-16

    申请人： Derryl D. J. Allman ,  Gayle W. Miller

    发明人： Derryl D. J. Allman ,  Gayle W. Miller

    IPC分类号： H01L27/06 ,  H01L21/225 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732

    CPC分类号： H01L29/66272 ,  H01L21/2255 ,  H01L29/0804

    摘要： A method for forming a bipolar emitter using doped SOG which employs diffusion instead of implanting, and which produces a shallow, low-resistance emitter using a variety of dopants besides boron and phosphorus. A layer of doped SOG is spun over a predefined base region. Portions of the SOG layer are defined for removal and removed, leaving the collector and emitter contact areas exposed. The SOG layer is densified and the dopants are driven into the base to form the emitter.

    摘要翻译： 使用掺杂SOG形成双极型发射体的方法，其使用扩散而不是植入，并且使用除硼和磷之外的各种掺杂剂产生浅的低电阻发射体。 在预定义的碱性区域上旋转一层掺杂的SOG。 SOG层的部分被限定为去除和去除，使集电极和发射极接触区域暴露。 SOG层被致密化并且掺杂剂被驱动到基底中以形成发射极。