公开(公告)号：US06467427B1

公开(公告)日：2002-10-22

申请号：US09710713

申请日：2000-11-10

申请人： Kuang-Chung Peng

发明人： Kuang-Chung Peng

IPC分类号： H01L21285

CPC分类号： C23C14/246 ,  H01L21/2855

摘要： A supplier of evaporation source material. The evaporation system that uses the source material supplier includes an evaporation chamber and a vacuum extraction system. The vacuum extraction system is connected to the evaporation chamber. The source material supplier, a movable evaporation boat and a wafer holder are housed inside the evaporation chamber. The source material supplier is on one of the sidewalls inside the evaporation chamber. The wafer holder is in the upper portion of the evaporation chamber. The wafer holder is responsible for holding a wafer requiring thin film deposition. The movable evaporation boat is in the lower portion of the evaporation chamber for holding evaporation source material. The source material supplier includes a revolving cassette wheel and a crucible under the cassette wheel. The revolving cassette wheel is partition by separating plates and an outer casing into a plurality of capsules with each capsule capable of holding a fixed amount of evaporation source material. When the cassette wheel rotates, the lowest capsule can deliver a lump of evaporation source material onto the crucible via a drop hole in the outer casing.

摘要翻译： 蒸发源材料供应商。 使用源材料供应商的蒸发系统包括蒸发室和真空抽提系统。 真空抽吸系统连接到蒸发室。 源材料供应商，可移动蒸发船和晶片保持器容纳在蒸发室内。 源材料供应商位于蒸发室内的一个侧壁上。 晶片支架位于蒸发室的上部。 晶片保持器负责保持需要薄膜沉积的晶片。 可移动蒸发舟皿位于用于保持蒸发源材料的蒸发室的下部。 源材料供应商包括旋转盒式磁盘和在盒式磁盘下方的坩埚。 旋转盒式轮通过将板和外壳分离成多个胶囊来分隔，每个胶囊能够保持固定量的蒸发源材料。 当盒式磁盘轮旋转时，最低的胶囊可以通过外壳中的下落孔将一团蒸发源材料输送到坩埚上。

公开(公告)号：US06624067B2

公开(公告)日：2003-09-23

申请号：US09782533

申请日：2001-02-13

申请人： Murty S. Polavarapu

发明人： Murty S. Polavarapu

IPC分类号： H01L21285

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/30604 ,  H01L21/32134

摘要： A process for selectively removing a silicon-containing material through use of a byproduct of a chemical vapor deposition is disclosed. The process includes fabricating an insulating film upon a silicon base layer such that the insulating film includes a cavity. A diffusion barrier layer is deposited into the cavity. The diffusion barrier layer is formed during a chemical vapor deposition which produces an alkyl halide as a byproduct. A photoresist layer is fabricated upon a silicon-containing material. A portion of the photoresist is removed, thereby exposing a portion of the silicon-containing material. The exposed portion of the silicon-containing material is removed with a chemical etch solution including the alkyl halide.

摘要翻译： 公开了通过使用化学气相沉积副产物来选择性除去含硅材料的方法。 该工艺包括在硅基层上制造绝缘膜，使得绝缘膜包括空腔。 扩散阻挡层被沉积到空腔中。 在化学气相沉积期间形成扩散阻挡层，其产生作为副产物的烷基卤化物。 在含硅材料上制造光致抗蚀剂层。 去除一部分光致抗蚀剂，从而暴露一部分含硅材料。 用包含烷基卤化物的化学蚀刻溶液去除含硅材料的暴露部分。

公开(公告)号：US06239028B1

公开(公告)日：2001-05-29

申请号：US09148089

申请日：1998-09-03

申请人： Brian A. Vaartstra

发明人： Brian A. Vaartstra

IPC分类号： H01L21285

CPC分类号： H01L21/28568

摘要： A method of forming an iridium-containing film on a substrate, such as a semiconductor wafer using complexes of the formula LyIrXz, wherein: each L group is independently a neutral or anionic ligand; each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N2, PX3, PR3, P(OR)3, AsX3, AsR3, As(OR)3, SbX3, SbR3, Sb(OR)3, NHxR3-x, CNR, and RCN, wherein R is an organic group and X is a halide; y=1 to 4; z=1 to 4; x=0 to 3.

公开(公告)号：US06426292B2

公开(公告)日：2002-07-30

申请号：US09790286

申请日：2001-02-22

申请人： Brian A. Vaartstra

发明人： Brian A. Vaartstra

IPC分类号： H01L21285

CPC分类号： H01L21/28568

摘要： A method of forming an iridium and platinum containing film on a substrate, such as a semiconductor wafer using complexes of the formula LyIrXz, wherein: each L group is independently a neutral or anionic ligand; each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N2, PX3, PR3, P(OR)3, AsX3, AsR3, As(OR)3, SbX3, SbR3, Sb(OR)3, NHxR3−x, CNR, and RCN, wherein R is an organic group and X is a halide; y=1 to 4; z=1 to 4; x=0 to 3.

摘要翻译： 在基底上形成铱和含铂膜的方法，例如使用式LyIrXz的配合物的半导体晶片，其中：每个L基团独立地为中性或阴离子配体; 每个Y基团独立地是选自CO，NO，CN，CS，N 2，PX 3，PR 3，P（OR）3，AsX 3，AsR 3，As（OR）3，SbX 3，SbR 3，Sb（ OR）3，NH x R 3-x，CNR和RCN，其中R是有机基团，X是卤化物; y = 1〜4; z = 1〜4; x = 0〜3。

公开(公告)号：US06177305B1

公开(公告)日：2001-01-23

申请号：US09213847

申请日：1998-12-17

申请人： Verne C. Hornback ,  Derryl D. J. Allman ,  Newell E. Chiesl

发明人： Verne C. Hornback ,  Derryl D. J. Allman ,  Newell E. Chiesl

IPC分类号： H01L21285

CPC分类号： H01L28/40 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/31604 ,  H01L28/56 ,  Y10S438/907

摘要： Techniques for fabricating metal-insulator-metal (MIM) capacitive structures by chemical vapor deposition (CVD) help avoid the formation of a porous metal oxide film at the interface between the lower electrode and the insulating layer. One method of fabricating an integrated circuit includes depositing a first titanium nitride electrode layer on a wafer by CVD and subsequently depositing an insulating layer on the first electrode. The insulating layer can comprise a material selected from the group consisting of titanium oxide (TiOx), titanium oxynitride (TiOxNy), titanium oxycarbonitride (TiOxNyCz) and silicon oxide (SiOx), and is deposited by CVD without exposing the first titanium nitride electrode to atmosphere. A second titanium nitride electrode layer also is deposited on the insulating layer by CVD. The various layers of the capacitive structure, including the insulating layer, can be deposited in situ in a single CVD chamber.

摘要翻译： 通过化学气相沉积（CVD）制造金属 - 绝缘体 - 金属（MIM）电容结构的技术有助于避免在下电极和绝缘层之间的界面处形成多孔金属氧化物膜。 制造集成电路的一种方法包括通过CVD沉积在晶片上的第一氮化钛电极层，并随后在第一电极上沉积绝缘层。 绝缘层可以包括选自氧化钛（TiO x），氮氧化钛（TiO x N y），碳氮氧化钛（TiO x N y C z）和氧化硅（SiO x）的材料，并且通过CVD沉积而不暴露第一氮化钛电极 大气层。 第二氮化钛电极层也通过CVD沉积在绝缘层上。 包括绝缘层的电容结构的各个层可以在单个CVD室中原位沉积。

公开(公告)号：US06387786B1

公开(公告)日：2002-05-14

申请号：US09733778

申请日：2000-12-08

申请人： Jeff Erhardt ,  Eric Paton

发明人： Jeff Erhardt ,  Eric Paton

IPC分类号： H01L21285

CPC分类号： H01L29/66507 ,  H01L29/4933

摘要： The present invention relates to a method of forming a self-aligned silicide (salicide) by siliciding a gate area prior to siliciding a source and drain area and/or spacer formation. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area that is advantageously thicker than silicide formations over the source and drain areas.

摘要翻译： 本发明涉及通过在将源极和漏极区域和/或间隔物形成硅化之前将栅极区域硅化来形成自对准硅化物（自对准硅化物）的方法。 该方法通过降低源极和漏极区域中的漏电流并降低栅极的多晶硅片电阻来提高晶体管的速度。 作为本方法的一个实施例的结果，在栅极区域上形成硅化物，其优选在源极和漏极区域上比硅化物层更厚。

公开(公告)号：US06281124B1

公开(公告)日：2001-08-28

申请号：US09146003

申请日：1998-09-02

申请人： Brian A. Vaartstra

发明人： Brian A. Vaartstra

IPC分类号： H01L21285

CPC分类号： H01L21/28556 ,  C23C16/18 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  Y10T29/41

摘要： A method of forming a film on a substrate using Group IVB, VB, or VIB metal complexes. The methods are particularly suitable for the preparation of semiconductor structures using chemical vapor deposition techniques and systems.

摘要翻译： 使用IVB，VB或VIB族金属络合物在基板上形成膜的方法。 该方法特别适用于使用化学气相沉积技术和系统制备半导体结构。

公开(公告)号：US06743668B2

公开(公告)日：2004-06-01

申请号：US10425242

申请日：2003-04-29

申请人： James K. Schaeffer, III ,  Mark V. Raymond ,  Bich-Yen Nguyen

发明人： James K. Schaeffer, III ,  Mark V. Raymond ,  Bich-Yen Nguyen

IPC分类号： H01L21285

CPC分类号： H01L21/28202 ,  H01L21/28194 ,  H01L21/3143 ,  H01L29/518

摘要： The invention relates to a semiconductor device and the process of forming a metal oxy-nitride gate dielectric layer or a metal-silicon oxy-nitride gate dielectric layer. The metal oxy-nitride or metal-silicon oxy-nitride dielectric layer comprises at least one of a metal, silicon, oxygen, and nitrogen atoms where the nitrogen to oxygen atomic ratio is at least 1:2. The metal oxy-nitride or metal-silicon oxy-nitride material has a higher dielectric constant in comparison with a silicon dioxide, providing similar or improved electrical characteristics with a thicker thickness. Other benefits include reduced leakage properties, improved thermal stability, and reduced capacitance versus voltage (CV) hysteresis offset.

摘要翻译： 本发明涉及一种半导体器件和形成金属氮氧化物栅介电层或金属硅氧氮化物栅介电层的工艺。 金属氮氧化物或金属硅氧氮化物电介质层包括金属，硅，氧和氮原子中的至少一种，其中氮与氧原子比至少为1:2。 与二氧化硅相比，金属氧化氮化物或金属硅氧氮化物材料具有更高的介电常数，提供具有较厚厚度的相似或改进的电气特性。 其他优点包括降低泄漏特性，改善热稳定性，降低电容对电压（CV）滞后补偿。

公开(公告)号：US06534375B2

公开(公告)日：2003-03-18

申请号：US09923406

申请日：2001-08-08

申请人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

发明人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

IPC分类号： H01L21285

CPC分类号： H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/91

摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

摘要翻译： 形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。 在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。 在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

公开(公告)号：US06333267B1

公开(公告)日：2001-12-25

申请号：US08400861

申请日：1995-03-08

申请人： Takashi Onishi ,  Eiji Iwamura ,  Seigo Yamamoto ,  Katsutoshi Takagi ,  Kazuo Yoshikawa

发明人： Takashi Onishi ,  Eiji Iwamura ,  Seigo Yamamoto ,  Katsutoshi Takagi ,  Kazuo Yoshikawa

IPC分类号： H01L21285

CPC分类号： H01L21/28008 ,  C23C14/165 ,  G02F1/136286 ,  G02F2001/136295

摘要： An active matrix type liquid crystal display, in which the reliability is enhanced by preventing the short-circuit and insulation breakdown of a gate insulating portion and the delay time of a gate bus line is shortened by reducing the resistivity of an interconnect film. The liquid crystal display of this type is manufactured by the steps of forming an interconnect/electrode film on a substrate by physical deposition; patterning the interconnect/electrode film; and anodic-oxidizing part or all of the interconnect/electrode film. In this method, the interconnect/electrode film is formed of an Al alloy containing at least one kind selected from a group consisting Fe, Co and rare earth elements in an amount of 0.1 to 10 at %; and the thickness of the anodic oxidation film is specified to be in the range of 200 Å or more.

摘要翻译： 通过降低互连膜的电阻率，缩短了通过防止栅绝缘部分的短路和绝缘击穿以及栅极总线延迟时间来提高可靠性的有源矩阵型液晶显示器。 这种液晶显示器通过以下步骤制造：通过物理沉积在衬底上形成互连/电极膜; 图案化互连/电极膜; 和阳极氧化部分或全部的互连/电极膜。 在该方法中，互连电极膜由含有0.1〜10原子％的Fe，Co和稀土元素中的至少一种的Al合金形成， 阳极氧化膜的厚度规定在200以上的范围内。