公开(公告)号：US08233312B2

公开(公告)日：2012-07-31

申请号：US12934745

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C11/24

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的第一N型半导体区域，设置在第一N型半导体区域上的P型半导体区域，设置在P型半导体区域上的栅极区域和围绕P型半导体区域的电隔离区域 型半导体区域和N型半导体区域。 二极管作为存储节点。 通过带之间的隧道效应，孔被聚集在浮体中，其被定义为第一储存状态; 通过PN结的正向偏压，空穴从浮体发射出来，或者电子被注入浮动体，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

公开(公告)号：US08409962B2

公开(公告)日：2013-04-02

申请号：US12937264

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang

发明人： Deyuan Xiao ,  Xiaolu Huang

IPC分类号： H01L21/20

CPC分类号： H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： present invention discloses a manufacturing method for a copper interconnection structure with MIM capacitor. The method firstly makes a copper conductive pattern in a copper interconnection structure and a copper through hole bolt connected with the copper conductive pattern; etch away an insulation layer around the copper through hole bolt and deposit a etch stop layer, so as to expose the top and side surface of the copper through hole bolt and part of the top surface of the copper conductive pattern; deposit a dielectric layer on the obtained structure and fill a protection material in the recession area of the obtained structure; etch a trench for receiving other copper conductive patterns; remove the protection material; plate copper in the recession area, and plate copper in the trench, so as to obtain a copper interconnection structure with MIM capacitor.

摘要翻译： 本发明公开了一种具有MIM电容器的铜互连结构的制造方法。 该方法首先在铜互连结构中形成铜导电图案，并与铜导电图案连接的铜通孔螺栓; 蚀刻围绕铜通孔螺栓的绝缘层，并沉积蚀刻停止层，以暴露铜通孔螺栓和铜导电图案的顶表面的一部分的顶表面和侧表面; 在所获得的结构上沉积介电层，并在所获得的结构的凹陷区域中填充保护材料; 蚀刻用于接收其它铜导电图案的沟槽; 取下保护材料; 在凹陷区域镀铜，并在沟槽中镀铜，以获得具有MIM电容器的铜互连结构。

公开(公告)号：US20120025267A1

公开(公告)日：2012-02-02

申请号：US13128439

申请日：2010-09-07

申请人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

发明人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/78612

摘要： A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

摘要翻译： 公开了一种用于消除浮体效应和自发热效应的SOI MOS器件。 该器件包括将有源栅极沟道耦合到Si衬底的连接层。 连接层在设备操作期间提供电气和热通道，可以消除浮体效应和自热效应。 详细公开了在Si活性通道和Si衬底之间具有SiGe连接器的MOS器件的实例，并提供了制造工艺。

公开(公告)号：US08710549B2

公开(公告)日：2014-04-29

申请号：US13128439

申请日：2010-09-07

申请人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

发明人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

IPC分类号： H01L29/66

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/78612

摘要： A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

摘要翻译： 公开了一种用于消除浮体效应和自发热效应的SOI MOS器件。 该器件包括将有源栅极沟道耦合到Si衬底的连接层。 连接层在设备操作期间提供电气和热通道，可以消除浮体效应和自热效应。 详细公开了在Si活性通道和Si衬底之间具有SiGe连接器的MOS器件的实例，并提供制造工艺。

公开(公告)号：US08422288B2

公开(公告)日：2013-04-16

申请号：US12937257

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C11/34

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的P型半导体区域，设置在P型半导体区域上的N型半导体区域，设置在N型半导体区域上的栅极区域和围绕P型半导体的电隔离区域 区域和N型半导体区域。 将浮体效应的二极管作为存储节点。 通过带之间的隧道效应，电子聚集在浮体中，其被定义为第一存储状态; 通过PN结的正向偏压，电子从浮体发出，或者将空穴注入到浮动体中，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

公开(公告)号：US20110292723A1

公开(公告)日：2011-12-01

申请号：US12937257

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C11/38 ,  H01L21/336 ,  H01L29/772

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的P型半导体区域，设置在P型半导体区域上的N型半导体区域，设置在N型半导体区域上的栅极区域和围绕P型半导体的电隔离区域 区域和N型半导体区域。 将浮体效应的二极管作为存储节点。 通过带之间的隧道效应，电子聚集在浮体中，其被定义为第一存储状态; 通过PN结的正向偏压，电子从浮体发出，或者将空穴注入到浮动体中，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

公开(公告)号：US20120018809A1

公开(公告)日：2012-01-26

申请号：US13127276

申请日：2010-09-08

申请人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

发明人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/1054

摘要： A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

摘要翻译： 公开了具有低浮动电荷和低自热效应的MOS器件。 该器件包括将有源栅极沟道耦合到Si衬底的连接层。 连接层在器件操作期间提供电和热通道，可以消除浮动效应和自热效应。 详细公开了在Si活性通道和Si衬底之间具有SiGe连接器的MOS器件的实例，并提供了制造工艺。

公开(公告)号：US20110291235A1

公开(公告)日：2011-12-01

申请号：US12937264

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang

发明人： Deyuan Xiao ,  Xiaolu Huang

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses a copper interconnection structure with MIM capacitor and a manufacturing method thereof. The method firstly makes a copper conductive pattern in a copper interconnection structure and a copper through hole bolt connected with the copper conductive pattern; etch away an insulation layer around the copper through hole bolt and deposit a etch stop layer, so as to expose the top and side surface of the copper through hole bolt and part of the top surface of the copper conductive pattern; deposit a dielectric layer on the obtained structure and fill a protection material in the recession area of the obtained structure; etch a trench for receiving other copper conductive patterns; remove the protection material; plate copper in the recession area, and plate copper in the trench, so as to obtain a copper interconnection structure with MIM capacitor.

摘要翻译： 本发明公开了一种具有MIM电容器的铜互连结构及其制造方法。 该方法首先在铜互连结构中形成铜导电图案，并与铜导电图案连接的铜通孔螺栓; 蚀刻围绕铜通孔螺栓的绝缘层，并沉积蚀刻停止层，以暴露铜通孔螺栓和铜导电图案的顶表面的一部分的顶表面和侧表面; 在所获得的结构上沉积介电层，并在所获得的结构的凹陷区域中填充保护材料; 蚀刻用于接收其它铜导电图案的沟槽; 取下保护材料; 在凹陷区域镀铜，并在沟槽中镀铜，以获得具有MIM电容器的铜互连结构。

公开(公告)号：US20110199842A1

公开(公告)日：2011-08-18

申请号：US12934745

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C7/00 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的第一N型半导体区域，设置在第一N型半导体区域上的P型半导体区域，设置在P型半导体区域上的栅极区域和围绕P型半导体区域的电隔离区域 型半导体区域和N型半导体区域。 二极管作为存储节点。 通过带之间的隧道效应，孔被聚集在浮体中，其被定义为第一储存状态; 通过PN结的正向偏压，空穴从浮体发射出来，或者电子被注入浮动体，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

公开(公告)号：US08969108B2

公开(公告)日：2015-03-03

申请号：US13881723

申请日：2011-02-10

申请人： Deyuan Xiao ,  Richard Rugin Chang

发明人： Deyuan Xiao ,  Richard Rugin Chang

IPC分类号： H01L29/06 ,  H01L33/64 ,  H01L33/00 ,  H01L21/20

CPC分类号： H01L33/385 ,  H01L21/2007 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/62 ,  H01L33/641

摘要： A light emitting diode (LED) and a forming method thereof are provided. The method for forming the LED includes: providing a semiconductor substrate (20) and a sapphire substrate (30) respectively, wherein a first bonding layer (21) is formed on the silicon substrate (20), and a sacrificial layer (32), an LED die (33) and a second bonding layer (35) are formed in turn on the sapphire substrate (30); bonding the first bonding layer (21) and the second bonding layer (35); removing the sacrificial layer (32) and lifting off the sapphire substrate (30). The method increases the effective lighting area of the LED, improves heat radiation, and enhances lighting efficiency.

摘要翻译： 提供一种发光二极管（LED）及其形成方法。 形成LED的方法包括：分别提供半导体衬底（20）和蓝宝石衬底（30），其中在硅衬底（20）上形成第一接合层（21）和牺牲层（32）， 依次在蓝宝石衬底（30）上形成LED管芯（33）和第二接合层（35）; 接合第一接合层（21）和第二接合层（35）; 去除牺牲层（32）并提起蓝宝石衬底（30）。 该方法增加了LED的有效照明面积，改善了散热，提高了照明效率。