公开(公告)号：US06014422A

公开(公告)日：2000-01-11

申请号：US82886

申请日：1998-05-21

申请人： Diane C. Boyd ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Paul A. Rabidoux

发明人： Diane C. Boyd ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Paul A. Rabidoux

IPC分类号： G03F7/038 ,  G03F7/20 ,  G21K5/00

CPC分类号： G03F7/70466 ,  G03F7/038 ,  G03F7/7035 ,  Y10S430/168

摘要： The present invention provides combining the advantages of hybrid resist with the unique properties of x-ray lithography to form high tolerance devices with x-ray pitch and to provide a means for varying the space width and fine tuning to account for process variations. Accordingly, a space width in the hybrid resist can be selectively printed by varying the mask-wafer gap distance, allowing more versatile structures to be formed and adjustments to be made for process changes such as resist composition and ion implant levels.

摘要翻译： 本发明将混合抗蚀剂的优点与x射线光刻的独特性质相结合，以形成具有x射线间距的高公差装置，并提供用于改变空间宽度和微调以解决工艺变化的装置。 因此，可以通过改变掩模 - 晶片间隙距离来选择性地印刷混合抗蚀剂中的空间宽度，从而允许形成更通用的结构，并且对诸如抗蚀剂组成和离子注入水平的工艺变化进行调整。

公开(公告)号：US06221562B1

公开(公告)日：2001-04-24

申请号：US09192137

申请日：1998-11-13

申请人： Diane C. Boyd ,  Toshiharu Furukawa ,  Steven J. Holmes ,  William H. Ma ,  Paul A. Rabidoux ,  David V. Horak

发明人： Diane C. Boyd ,  Toshiharu Furukawa ,  Steven J. Holmes ,  William H. Ma ,  Paul A. Rabidoux ,  David V. Horak

IPC分类号： G03F700

CPC分类号： H01L21/0337 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/32139

摘要： An image reversal method of turning hybrid photoresist spaces into resist lines for sub-feature size applications. The sub-feature size space width of the high resolution hybrid photoresist is largely independent of the lithographic process and mask reticles. These sub-feature size spaces formed by the hybrid resist are then turned into sub-feature size lines using Spin-On-Glass, SOG. The SOG is first coated over the entire patterned hybrid resist to fill in the hybrid spaces and cover the photoresist. SOG is then recessed back to expose the photoresist layer. The exposed photoresist is then removed. The sub-feature size lines are then left behind as a mask to pattern the same onto the underlying films on the substrate.

摘要翻译： 将混合光致抗蚀剂空间转换成用于子特征尺寸应用的抗蚀剂线的图像反转方法。 高分辨率混合光致抗蚀剂的子特征尺寸空间宽度在很大程度上独立于光刻工艺和掩模掩模版。 然后，使用旋转玻璃，SOG将由混合抗蚀剂形成的这些子特征尺寸空间变成子特征尺寸线。 SOG首先涂覆在整个图案化的混合抗蚀剂上以填充混合空间并覆盖光致抗蚀剂。 然后将SOG凹进来露出光致抗蚀剂层。 然后除去曝光的光致抗蚀剂。 然后将子特征尺寸线作为掩模留下以将其图案化到衬底上的下面的膜上。

公开(公告)号：US06531724B1

公开(公告)日：2003-03-11

申请号：US09686740

申请日：2000-10-10

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L29772

CPC分类号： H01L21/76897 ,  H01L21/76888 ,  H01L21/76895

摘要： A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.

摘要翻译： 一种用于在晶体管中形成栅极导体帽的方法，包括以下步骤：a）形成多晶硅栅极导体; b）掺杂多晶硅栅极; c）掺杂扩散区域; 以及d）通过从选择性氮化物沉积和选择性表面氮化中选择的氮化方法来封盖栅极导体。 所得到的晶体管可以包括封盖栅极导体和无边界扩散接触，其中通过选择性氮化物沉积和选择性表面氮化中选择的氮化方法发生封盖，并且其中在氮化方法期间掩模一部分栅极导体以留下开口 接触区域用于局部互连或门接触。

公开(公告)号：US06440801B1

公开(公告)日：2002-08-27

申请号：US09604901

申请日：2000-06-28

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

IPC分类号： H01L21336

CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

公开(公告)号：US06221704B1

公开(公告)日：2001-04-24

申请号：US09089650

申请日：1998-06-03

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James S. Nakos ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James S. Nakos ,  Paul A. Rabidoux

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/823842 ,  H01L29/66575

摘要： Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a first conductive-forming layer on the first insulating layer; forming a second conductive layer on the first conductive-forming layer; forming a second insulating layer on the second conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the second conductive layer; depositing a third insulating material through the opening over the conductive layer; planarizing the second insulating layer and the third insulating material; removing the second insulating layer, the first conductive-forming layer and second conductive layer and the first insulating layer except beneath the third insulating material; and forming source/drain regions in the substrate.

公开(公告)号：US5945707A

公开(公告)日：1999-08-31

申请号：US56903

申请日：1998-04-07

申请人： Gary B. Bronner ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Jack A. Mandelman ,  Paul A. Rabidoux

发明人： Gary B. Bronner ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Jack A. Mandelman ,  Paul A. Rabidoux

IPC分类号： H01L21/8242 ,  H01L29/72

CPC分类号： H01L27/10876 ,  H01L27/10861 ,  H01L27/10891

摘要： A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.

摘要翻译： 公开了一种在副光刻槽中形成有槽栅的存储单元及其制造方法。 凹槽延伸通道长度以包括凹槽侧壁和凹槽的宽度。 沿着栅极侧壁的通道的侧壁部分具有比沿着栅极底部宽度定位的底部通道部分长度更大的长度。 因此，存储器件主要由侧壁通道部分而不是底部通道部分控制。 沟槽可以是通过两步蚀刻形成的阶梯槽，以进一步增加沟道长度，并且可以沿着栅极导体宽度形成为中心。

公开(公告)号：US06759315B1

公开(公告)日：2004-07-06

申请号：US09224759

申请日：1999-01-04

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L218238

CPC分类号： H01L21/76897 ,  H01L21/76888 ,  H01L21/76895

摘要： A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.

摘要翻译： 在晶体管中形成修整栅极的方法包括以下步骤：在半导体衬底上形成多晶硅栅极导体，并通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法来修整多晶硅部分。 修整步骤可以选择性地补偿n沟道和p沟道器件。 此外，修整膜可以任选地通过从各向异性和各向同性蚀刻中选择的方法去除。 此外，可以通过生长膜的各向异性蚀刻形成栅极导体间隔物。 所得到的晶体管可以包括栅极导体的经修剪的多晶硅部分，其中通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法进行修整。

公开(公告)号：US06387783B1

公开(公告)日：2002-05-14

申请号：US09299267

申请日：1999-04-26

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L2128

CPC分类号： H01L29/42316 ,  H01L21/28581

摘要： Methods for forming a T-gate on a substrate are provided that employ a hybrid resist. The hybrid resist specifically is employed to define a base of the T-gate on the substrate with very high resolution. To define a base of the T-gate, a hybrid resist layer is deposited on the substrate. A mask having a reticle feature with an edge is provided and is positioned above the hybrid resist layer so that the edge of the reticle feature is above a desired location for the base of the T-gate. Thereafter, the hybrid resist layer is exposed to radiation through the mask, and the exposed hybrid resist layer is developed to define an opening therein for the base of the T-gate. Preferably the loop feature formed in the hybrid resist layer by the reticle feature during exposure is trimmed. The T-gate may be completed by employing any known T-gate fabrication techniques.

摘要翻译： 提供了在衬底上形成T形栅的方法，其采用混合抗蚀剂。 采用混合抗蚀剂专门用于以非常高的分辨率在衬底上限定T形栅极的基极。 为了限定T栅极的基极，在衬底上沉积混合抗蚀剂层。 提供了具有边缘的掩模版特征的掩模，并且位于混合抗蚀剂层之上，使得掩模版特征的边缘高于用于T形栅极的基底的期望位置。 此后，混合抗蚀剂层通过掩模暴露于辐射，并且暴露的混合抗蚀剂层被显影以在T形栅极的底部限定开口。 优选地，在曝光期间通过掩模版特征在混合抗蚀剂层中形成的环形特征被修整。 T栅极可以通过采用任何已知的T栅极制造技术来完成。

公开(公告)号：US06303272B1

公开(公告)日：2001-10-16

申请号：US09192140

申请日：1998-11-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： G03C500

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L21/76897 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/451 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/48 ,  H01L2924/00

摘要： A method for forming contacts on an integrated circuit that are self-aligned with the wiring patterns of the integrated circuit. In the method a thicker lower layer of a first material and a thinner upper layer of a second material are formed on a substrate. The features of the metal wiring is patterned first on the upper layer. The wiring pattern trenches are etched through the thinner surface layer, and partially through the second, thicker layer. After the wiring pattern is etched, the contacts for the wiring layer are printed as line/space patterns which intersect the wiring pattern. The contact pattern is etched into the lower, thicker layer with an etch process that is selective to the upper thinner layer. The contact is only formed at the intersection point of the wiring image with the contact image, therefore the contact is self-aligned to the metal.

摘要翻译： 一种用于在与集成电路的布线图形自对准的集成电路上形成触点的方法。 在该方法中，在衬底上形成较厚的第一材料的下层和较薄的第二材料的上层。 金属布线的特征首先在上层形成。 通过更薄的表面层蚀刻布线图案沟槽，并部分地穿过第二较厚的层。 在布线图案被蚀刻之后，布线层的触点被印刷为与布线图案相交的线/间隔图形。 通过对上部较薄层选择性的蚀刻工艺将接触图案蚀刻到下部更厚的层中。 接触仅在接线图像与接触图像的交点处形成，因此触点与金属自对准。

公开(公告)号：US06184041B2

公开(公告)日：2001-02-06

申请号：US09078118

申请日：1998-05-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： G03F720

CPC分类号： G03F7/039 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/095

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a method to form spaces in hybrid resist with varying widths. In particular, the preferred method facilitates the formation of spaces with different widths by using mask shapes (either openings or lines) that are smaller than the diffraction limit of the photolithography tool. Diffraction effects at these dimensions reduce the light intensity reaching the resist surface such that the hybrid resist receives an intermediate exposure. These portions of hybrid resist that receive an intermediate exposure are soluble in developer and thus develop away to form spaces in the hybrid resist. Thus, spaces in the hybrid resist of varying widths can be formed.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种在具有不同宽度的混合抗蚀剂中形成空间的方法。 特别地，优选的方法通过使用小于光刻工具的衍射极限的掩模形状（开口或线）来促进形成具有不同宽度的空间。 在这些尺寸下的衍射效应降低了到达抗蚀剂表面的光强度，使得混合抗蚀剂接受中间曝光。 接受中间曝光的混合抗蚀剂的这些部分可溶于显影剂中，因此显影掉以在混合抗蚀剂中形成空间。 因此，可以形成不同宽度的混合抗蚀剂中的空间。