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公开(公告)号：US08966019B2
公开(公告)日：2015-02-24
申请号：US12822222
申请日：2010-06-24
IPC分类号： G06F15/177 , G06F9/54 , G06F3/00 , H02J3/14
CPC分类号： G06F9/541 , Y10T307/931
摘要： A method, apparatus, and computer program product for running software on an adapter. In response to a connection of a hardware interface for the adapter with a current host computer, a processor unit in the adapter determines whether a set of protocols for communicating with the current host computer to access resources is present on the adapter. In response to the set of protocols being absent on the adapter, the processor unit obtains the set of protocols from the current host computer. The processor unit identifies a set of available resources in the current host computer for use by the adapter using the set of protocols. The processor unit runs software stored on a set of storage devices in the adapter using the set of available resources identified for use by the adapter.
摘要翻译： 一种用于在适配器上运行软件的方法，装置和计算机程序产品。 响应于用于适配器的硬件接口与当前主机计算机的连接，适配器中的处理器单元确定用于与当前主机计算机通信以访问资源的一组协议是否存在于适配器上。 响应于适配器上不存在的协议集合，处理器单元从当前的主计算机获得一组协议。 处理器单元识别当前主机中的一组可用资源，供适配器使用该协议集合使用。 处理器单元使用识别供适配器使用的一组可用资源运行存储在适配器中的一组存储设备上的软件。
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公开(公告)号：US20110320573A1
公开(公告)日：2011-12-29
申请号：US12822222
申请日：2010-06-24
IPC分类号： G06F15/177 , G06F15/16
CPC分类号： G06F9/541 , Y10T307/931
摘要： A method, apparatus, and computer program product for running software on an adapter. In response to a connection of a hardware interface for the adapter with a current host computer, a processor unit in the adapter determines whether a set of protocols for communicating with the current host computer to access resources is present on the adapter. In response to the set of protocols being absent on the adapter, the processor unit obtains the set of protocols from the current host computer. The processor unit identifies a set of available resources in the current host computer for use by the adapter using the set of protocols. The processor unit runs software stored on a set of storage devices in the adapter using the set of available resources identified for use by the adapter.
摘要翻译： 一种用于在适配器上运行软件的方法，装置和计算机程序产品。 响应于用于适配器的硬件接口与当前主机计算机的连接，适配器中的处理器单元确定用于与当前主机计算机通信以访问资源的一组协议是否存在于适配器上。 响应于适配器上不存在的协议集合，处理器单元从当前的主计算机获得一组协议。 处理器单元识别当前主机中的一组可用资源，供适配器使用该协议集合使用。 处理器单元使用识别供适配器使用的一组可用资源运行存储在适配器中的一组存储设备上的软件。
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3.发明申请Two Partition Accelerator and Application of Tiered Flash to Cache Hierarchy in Partition Acceleration 失效分区加速器的两个分区加速器和应用分区加速中的缓存层次结构公开(公告)号：US20110022803A1
公开(公告)日：2011-01-27
申请号：US12508621
申请日：2009-07-24
申请人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
发明人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
CPC分类号： G06F12/0811 , G06F2212/1024 , G06F2212/1032
摘要： An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.
摘要翻译： 提供了一种用于从包括在处理节点中的一组处理核心识别禁用的处理核心和活动处理核心的方法。 每个处理核心被分配一个高速缓冲存储器。 该方法扩展了分配给活动处理核心的高速缓存存储器的存储器映射，以包括分配给禁用处理核心的高速缓存存储器。 由第一进程使用的第一数据量由活动处理核存储到分配给活动处理核的高速缓冲存储器。 第二数据量由活动处理核心使用扩展存储器映射存储到分配给非活动处理核心的缓存存储器。
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公开(公告)号：US20120042131A1
公开(公告)日：2012-02-16
申请号：US12856682
申请日：2010-08-15
申请人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
发明人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
CPC分类号： G06F12/0811 , G06F12/0284 , G06F2212/502 , G06F2212/604
摘要： An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.
摘要翻译： 提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。 该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于 多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。 该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小 正在由第二处理核心执行。
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公开(公告)号：US08438338B2
公开(公告)日：2013-05-07
申请号：US12856682
申请日：2010-08-15
申请人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
发明人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
IPC分类号： G06F12/02
CPC分类号： G06F12/0811 , G06F12/0284 , G06F2212/502 , G06F2212/604
摘要： An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.
摘要翻译： 提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。 该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于 多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。 该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小 正在由第二处理核心执行。
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6.发明授权Two partition accelerator and application of tiered flash to cache hierarchy in partition acceleration 失效两个分区加速器和分层闪存的应用在分区加速中缓存层次结构公开(公告)号：US08417889B2
公开(公告)日：2013-04-09
申请号：US12508621
申请日：2009-07-24
申请人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
发明人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F2212/1024 , G06F2212/1032
摘要： An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.
摘要翻译： 提供了一种用于从包括在处理节点中的一组处理核心识别禁用的处理核心和活动处理核心的方法。 每个处理核心被分配一个高速缓冲存储器。 该方法扩展了分配给活动处理核心的高速缓存存储器的存储器映射，以包括分配给禁用处理核心的高速缓存存储器。 由第一进程使用的第一数据量由活动处理核存储到分配给活动处理核的高速缓冲存储器。 第二数据量由活动处理核心使用扩展存储器映射存储到分配给非活动处理核心的缓存存储器。
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7.发明授权Ensuring affinity at all affinity domains by folding at each affinity level possible for a partition spanning multiple nodes 失效通过折叠跨越多个节点的分区的每个亲和力级别来确保所有关联性域的亲和力公开(公告)号：US08631132B2
公开(公告)日：2014-01-14
申请号：US13439604
申请日：2012-04-04
IPC分类号： G06F15/173
CPC分类号： G06F9/5083 , G06F9/5066
摘要： The different illustrative embodiments provide a method, apparatus, and computer program product for folding at each affinity level for a partition spanning multiple nodes. In one illustrative embodiment, a method is provided for identifying a number of domains in a number of affinity levels. A lightest loaded domain is identified in the number of domains identified. A number of nodes are identified in the lightest loaded domain identified. A lightest loaded node is identified in the number of nodes. A lightest loaded processing unit on the lightest loaded node is identified and the lightest loaded processing unit is folded.
摘要翻译： 不同的说明性实施例提供了用于在跨越多个节点的分区的每个关联级别折叠的方法，装置和计算机程序产品。 在一个说明性实施例中，提供了一种用于识别多个亲和度级别中的多个域的方法。 识别的域数确定了最轻的域。 在识别的最轻的加载域中识别出许多节点。 在节点数中识别最轻的加载节点。 识别最轻负载节点上的最轻载处理单元，并将轻载处理单元折叠。
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8.发明授权Ensuring affinity at all affinity domains by folding at each affinity level possible for a partition spanning multiple nodes 失效通过在跨越多个节点的分区的每个亲和力级别折叠来确保所有关联性域的亲和力公开(公告)号：US08224955B2
公开(公告)日：2012-07-17
申请号：US12437035
申请日：2009-05-07
IPC分类号： G06F15/173
CPC分类号： G06F9/5083 , G06F9/5066
摘要： The different illustrative embodiments provide a method, apparatus, and computer program product for folding at each affinity level for a partition spanning multiple nodes. In one illustrative embodiment, a method is provided for identifying a number of domains in a number of affinity levels. A lightest loaded domain is identified in the number of domains identified. A number of nodes are identified in the lightest loaded domain identified. A lightest loaded node is identified in the number of nodes. A lightest loaded processing unit on the lightest loaded node is identified and the lightest loaded processing unit is folded.
摘要翻译： 不同的说明性实施例提供了用于在跨越多个节点的分区的每个关联级别折叠的方法，装置和计算机程序产品。 在一个说明性实施例中，提供了一种用于识别多个亲和度级别中的多个域的方法。 识别的域数确定了最轻的域。 在识别的最轻的加载域中识别出许多节点。 在节点数中识别最轻的加载节点。 识别最轻负载节点上的最轻载处理单元，并将轻载处理单元折叠。
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公开(公告)号：US20100251239A1
公开(公告)日：2010-09-30
申请号：US12409992
申请日：2009-03-24
IPC分类号： G06F9/44
CPC分类号： G06F11/3612 , G06F11/3604 , G06F11/3644
摘要： Methods, systems, and products for lock tracing at a component level. The method includes associating one or more locks with a component of the operating system; initiating lock tracing for the component; and instrumenting the component-associated locks with lock tracing program instructions in response to initiating lock tracing. The locks are selected from a group of locks configured for use by an operating system and individually comprise locking code. The component lock tracing may be static or dynamic.
摘要翻译： 在组件级别进行锁跟踪的方法，系统和产品。 该方法包括将一个或多个锁与操作系统的组件相关联; 启动组件的锁跟踪; 并使用锁跟踪程序指令对组件相关的锁进行检测，以响应启动锁跟踪。 锁是从被配置为由操作系统使用的锁组中选择的，并且分别包括锁定码。 组件锁跟踪可以是静态或动态的。
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10.发明申请Method for Debugging a Hang Condition in a Process Without Affecting the Process State 失效在不影响过程状态的情况下调试挂起条件的方法公开(公告)号：US20100174946A1
公开(公告)日：2010-07-08
申请号：US12348079
申请日：2009-01-02
CPC分类号： G06F11/3644 , G06F9/3851 , G06F9/3863
摘要： Embodiments of the invention are associated with an application process that comprises multiple threads, wherein threads of the process are disposes to run on a data processing system, and each thread can have a user mode or a kernel mode machine state, or both, selectively, when it is running. An embodiment directed to a method comprises the steps of allocating a specified memory location for each of the threads, and responsive to a given thread entering a sleep state, selectively saving the kernel mode machine state of the given thread in the specified memory location for the given thread. The saved machine state comprises the state of the given thread immediately prior to the given thread entering the sleep state. In response to detecting a hang condition in the operation of the process, a debugger is attached to the process to access at least one of the saved user mode machine states. The method further includes analyzing information provided by the at least one accessed machine state to determine the cause of the hang condition, and restoring the original state upon detachment, so the debugger attachment is completely transparent to the target process.
摘要翻译： 本发明的实施例与包括多个线程的应用过程相关联，其中该过程的线程被配置为在数据处理系统上运行，并且每个线程可以选择性地具有用户模式或内核模式机器状态， 当它运行时。 针对方法的实施例包括以下步骤：为每个线程分配指定的存储器位置，并且响应于给定的线程进入休眠状态，选择性地将给定线程的内核模式机器状态保存在指定的存储器位置中以供 给线程 保存的机器状态包括在给定线程进入睡眠状态之前的给定线程的状态。 响应于检测到处理的操作中的挂起状况，调试器被附加到该过程以访问保存的用户模式机器状态中的至少一个。 该方法还包括分析由至少一个访问机器状态提供的信息以确定挂起状况的原因，以及在拆卸时恢复原始状态，因此调试器附件对于目标进程是完全透明的。
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