-
公开(公告)号：US20120239841A1
公开(公告)日：2012-09-20
申请号：US13049694
申请日：2011-03-16
IPC分类号： G06F13/14
CPC分类号： G06F13/4282
摘要： A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.
摘要翻译： 提供了一种方法。 通过单线总线的IC的输入引脚接收通信，其中通信包括命令字节。 如果命令字节是初始化命令字节，则执行自寻址操作以识别IC的总线地址。 或者，如果命令字节是数据移动命令字节，则执行数据移动操作。 当执行数据移动操作时，如果来自命令字节的操作地址与总线地址匹配，则IC的总线接口从透明模式设置为操作模式，使得可以访问在命令字节中识别的寄存器和数据移动 可以执行寄存器。
-
2.发明授权Hybrid delta-sigma/SAR analog to digital converter and methods for using such 有权混合Δ-Σ/ SAR模数转换器及其使用方法公开(公告)号：US07504977B2
公开(公告)日：2009-03-17
申请号：US11738566
申请日：2007-04-23
IPC分类号： H03M3/00
摘要： Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.
摘要翻译： 公开了用于捕获数据的各种系统和方法。 例如，本发明的一些实施例提供了使用基于Δ-Σ的模数转换器执行第一模数转换的方法，以及使用基于SAR的模数转换器执行第二模数转换。 Δ-Σ转换器提供转换结果的第一部分，并且基于SAR的模数转换器提供转换结果的第二部分。 所述方法还包括将转换结果的第一部分与转换结果的第二部分组合以产生组合转换结果。
-
公开(公告)号：US07592867B2
公开(公告)日：2009-09-22
申请号：US11732357
申请日：2007-04-03
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F3/45632 , H03F2203/45082 , H03F2203/45101 , H03F2203/45292 , H03F2203/45681
摘要： A differential amplifier includes a differential input pair (2A) coupled to a folded cascode stage (2B) and a common mode feedback circuit (34) including a tracking circuit (30A) coupled to first (Vout−) and second (Vout+) outputs of the folded cascode stage (2B). The first and second outputs are coupled to first terminals of first (31A) and second (31B) tracking capacitors which have second terminals on which a first common mode output signal (VCM1) is produced and also are coupled to first terminals of third (32A) and fourth (32B) tracking capacitors, respectively, which have second terminals on which a second common mode output signal (VCM2) is produced. The first and third tracking capacitors are discharged by first (27A) and second (27B) switches that directly couple the first and second outputs to first and second inputs of a common mode feedback amplifier (4). A desired common mode output voltage (VCM-IN) is applied to a third input of the common mode feedback amplifier. The switches are opened to cause the first and second common mode output voltages to be generated, causing a common mode feedback control signal (VCMFB) to be generated for biasing the folded cascode stage.
摘要翻译： 差分放大器包括耦合到折叠共源共栅级（2B）的差分输入对（2A）和共模反馈电路（34），其包括耦合到第一（Vout-）和第二（Vout +）输出的跟踪电路 折叠共源共栅阶段（2B）。 第一和第二输出耦合到具有第二端子的第一（31A）和第二（31B）跟踪电容器的第一端子，第二端子产生第一共模输出信号（VCM1），并且还耦合到第三端子（32A）的第一端子 ）和第四（32B）个跟踪电容器，它们具有产生第二共模输出信号（VCM2）的第二端子。 第一和第三跟踪电容器通过将第一和第二输出直接耦合到共模反馈放大器（4）的第一和第二输入的第一（27A）和第二（27B）开关来放电。 所需的共模输出电压（VCM-IN）被施加到共模反馈放大器的第三输入端。 打开开关以产生第一和第二共模输出电压，从而产生共模反馈控制信号（VCMFB）以偏置折叠共源共栅级。
-
公开(公告)号：US20080246543A1
公开(公告)日：2008-10-09
申请号：US11732357
申请日：2007-04-03
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F3/45632 , H03F2203/45082 , H03F2203/45101 , H03F2203/45292 , H03F2203/45681
摘要： A differential amplifier includes a differential input pair (2A) coupled to a folded cascode stage (2B) and a common mode feedback circuit (34) including a tracking circuit (30A) coupled to first (Vout−) and second (Vout+) outputs of the folded cascode stage (2B). The first and second outputs are coupled to first terminals of first (31A) and second (31B) tracking capacitors which have second terminals on which a first common mode output signal (VCM1) is produced and also are coupled to first terminals of third (32A) and fourth (32B) tracking capacitors, respectively, which have second terminals on which a second common mode output signal (VCM2) is produced. The first and third tracking capacitors are discharged by first (27A) and second (27B) switches that directly couple the first and second outputs to first and second inputs of a common mode feedback amplifier (4). A desired common mode output voltage (VCM-IN) is applied to a third input of the common mode feedback amplifier. The switches are opened to cause the first and second common mode output voltages to be generated, causing a common mode feedback control signal (VCMFB) to be generated for biasing the folded cascode stage.
摘要翻译： 差分放大器包括耦合到折叠共源共栅级（2B）的差分输入对（2A）和包括耦合到第一（Vout）的跟踪电路（30A）的共模反馈电路（34） SUP>）和第二（Vout + SUP））输出。 第一和第二输出耦合到具有第二端子的第一（31A）和第二（31B）跟踪电容器的第一端子，第二端子产生第一共模输出信号（V SUB CM1） 也分别耦合到第三（32A）和第四（32B）个跟踪电容器的第一端子，它们具有产生第二共模输出信号（V SUB CM2）的第二端子。 第一和第三跟踪电容器通过将第一和第二输出直接耦合到共模反馈放大器（4）的第一和第二输入的第一（27A）和第二（27B）开关放电。 所需的共模输出电压（V SUB-IN IN）被施加到共模反馈放大器的第三输入端。 打开开关以产生第一和第二共模输出电压，从而产生用于偏置折叠共源共栅级的共模反馈控制信号（V SUB CMBB）。
-
5.发明申请Hybrid Delta-Sigma/SAR Analog to Digital Converter and Methods for Using Such 有权混合Delta-Sigma / SAR模数转换器及其使用方法公开(公告)号：US20080258951A1
公开(公告)日：2008-10-23
申请号：US11738566
申请日：2007-04-23
IPC分类号： H03M3/00
摘要： Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.
摘要翻译： 公开了用于捕获数据的各种系统和方法。 例如，本发明的一些实施例提供了使用基于Δ-Σ的模数转换器执行第一模数转换的方法，以及使用基于SAR的模数转换器执行第二模数转换。 Δ-Σ转换器提供转换结果的第一部分，并且基于SAR的模数转换器提供转换结果的第二部分。 所述方法还包括将转换结果的第一部分与转换结果的第二部分组合以产生组合转换结果。
-
公开(公告)号：US09003096B2
公开(公告)日：2015-04-07
申请号：US13049694
申请日：2011-03-16
CPC分类号： G06F13/4282
摘要： A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.
摘要翻译： 提供了一种方法。 通过单线总线的IC的输入引脚接收通信，其中通信包括命令字节。 如果命令字节是初始化命令字节，则执行自寻址操作以识别IC的总线地址。 或者，如果命令字节是数据移动命令字节，则执行数据移动操作。 当执行数据移动操作时，如果来自命令字节的操作地址与总线地址匹配，则IC的总线接口从透明模式设置为操作模式，使得可以访问在命令字节中识别的寄存器和数据移动 可以执行寄存器。
-
公开(公告)号：US07595676B2
公开(公告)日：2009-09-29
申请号：US11880582
申请日：2007-07-23
申请人： Dimitar T. Trifonov
发明人： Dimitar T. Trifonov
IPC分类号： H03K3/00
CPC分类号： H03K5/2481 , H03K3/3565 , H03K5/088
摘要： A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin−), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref−) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load. An output stage (6A) produces a comparator output voltage (Vout) in response to an output (V2) produced by the first and second (11) differential input stages. A switching threshold of the comparator is determined by a difference between the first and second reference voltages.
-
8.发明申请Low-noise, wide offset range, programmable input offset amplifier front end and method 有权低噪声，宽偏移范围，可编程输入失调放大器前端和方法公开(公告)号：US20100019842A1
公开(公告)日：2010-01-28
申请号：US12229278
申请日：2008-08-21
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45197 , H03F3/45928 , H03F3/72 , H03F2203/45101 , H03F2203/45482 , H03F2203/45494 , H03F2203/45616 , H03F2203/45678 , H03F2203/45681
摘要： A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin−) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (−) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.
摘要翻译： 可编程偏移放大器包括具有与第一（Vin +）和第二（Vin-）输入电压耦合的差分连接的源极和第一（M1）和第二（M2）输入晶体管。 尾电流（Itail1）在第一和第二输入晶体管之间共享。 第一（M3）和第二（M4）负载装置分别耦合在参考电压和第一和第二输入晶体管的漏极之间。 输出级（13）具有耦合到第二输入晶体管的漏极的第一输入（+）和耦合到第一输入晶体管的漏极的第二输入（ - ）。 可编程电压变化在可编程输入偏移电路的输入元件上产生，以引起与输入晶体管的电极相关联的偏移电压的变化，其被反射回到放大器输入端以提供大的可编程输入参考偏移电压。
-
公开(公告)号：US20090073011A1
公开(公告)日：2009-03-19
申请号：US11901355
申请日：2007-09-17
IPC分类号： H03M1/06
摘要： Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on measured gain error in a memory (44). The gain-adjusted LSB size is applied to the digital filter to cause gain-adjusted LSB size values to be added to or subtracted from accumulated content of the digital filter in accordance with a first or second state, respectively, of the comparator (30) during each cycle of the ADC. The final accumulated content after all required cycles of the ADC is a gain-corrected digital output signal (Dout(gain-corrected)).
摘要翻译： 通过将经增益调整的LSB大小基于测量的增益误差存储在存储器（44）中，在包括积分器（17），比较器（30）和数字滤波器（37）的ADC芯片中校正增益误差。 经增益调整的LSB大小被施加到数字滤波器，以使得根据比较器（30）的第一或第二状态，增加经调整的LSB大小值被添加到数字滤波器的累加内容或从累积内容中减去， 在ADC的每个周期。 ADC所需的所有周期之后的最终累加内容是增益校正的数字输出信号（Dout（增益校正））。
-
公开(公告)号：US20090027086A1
公开(公告)日：2009-01-29
申请号：US11880582
申请日：2007-07-23
申请人： Dimitar T. Trifonov
发明人： Dimitar T. Trifonov
IPC分类号： H03K5/22
CPC分类号： H03K5/2481 , H03K3/3565 , H03K5/088
摘要： A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin−), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref−) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load. An output stage (6A) produces a comparator output voltage (Vout) in response to an output (V2) produced by the first and second (11) differential input stages. A switching threshold of the comparator is determined by a difference between the first and second reference voltages.
摘要翻译： 比较器（12A，12B）包括第一差分输入级（10），包括第一（MN2）和第二输入晶体管（MN3）和负载（MP9，MP10），第一输入晶体管（MN2） 和分别耦合到第一输入电压（Vin-），第一尾电流源和负载的漏极。 第二输入晶体管具有耦合到第二输入电压（Vin +）和第一尾电流源的栅极和源极。 第二差分输入级（11）包括第三（MN4）和第四（MN5）输入晶体管，第三输入晶体管分别具有耦合到第一参考电压（Vref +）和第二尾电流源的栅极和源极。 第四输入晶体管（MN5）分别具有耦合到第二参考电压（Vref-）和第二尾电流源的栅极和源极。 第三和第四输入晶体管的漏极耦合到负载。 输出级（6A）响应于由第一和第二（11）差分输入级产生的输出（V2）产生比较器输出电压（Vout）。 比较器的切换阈值由第一和第二参考电压之间的差确定。
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.019 秒)
