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1.发明申请Hybrid Delta-Sigma/SAR Analog to Digital Converter and Methods for Using Such 有权混合Delta-Sigma / SAR模数转换器及其使用方法公开(公告)号：US20080258951A1
公开(公告)日：2008-10-23
申请号：US11738566
申请日：2007-04-23
IPC分类号： H03M3/00
摘要： Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.
摘要翻译： 公开了用于捕获数据的各种系统和方法。 例如，本发明的一些实施例提供了使用基于Δ-Σ的模数转换器执行第一模数转换的方法，以及使用基于SAR的模数转换器执行第二模数转换。 Δ-Σ转换器提供转换结果的第一部分，并且基于SAR的模数转换器提供转换结果的第二部分。 所述方法还包括将转换结果的第一部分与转换结果的第二部分组合以产生组合转换结果。
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2.发明授权Hybrid delta-sigma/SAR analog to digital converter and methods for using such 有权混合Δ-Σ/ SAR模数转换器及其使用方法公开(公告)号：US07504977B2
公开(公告)日：2009-03-17
申请号：US11738566
申请日：2007-04-23
IPC分类号： H03M3/00
摘要： Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.
摘要翻译： 公开了用于捕获数据的各种系统和方法。 例如，本发明的一些实施例提供了使用基于Δ-Σ的模数转换器执行第一模数转换的方法，以及使用基于SAR的模数转换器执行第二模数转换。 Δ-Σ转换器提供转换结果的第一部分，并且基于SAR的模数转换器提供转换结果的第二部分。 所述方法还包括将转换结果的第一部分与转换结果的第二部分组合以产生组合转换结果。
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3.发明申请Integrating/SAR ADC and method with low integrator swing and low complexity 有权集成/ SAR ADC和低积分摆幅和低复杂度的方法公开(公告)号：US20080258959A1
公开(公告)日：2008-10-23
申请号：US12072968
申请日：2008-02-29
IPC分类号： H03M1/12
摘要： A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (ΔVbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (ΔVbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue−Vref or 2×Vresidue+Vref.
摘要翻译： 可重新配置电路（10）包括具有用于选择性地将输入电容器（C 0,1,2,3,6,7）和积分电容器（C 4,5）耦合到端子的开关（SW1-6）的积分器（30） 用于操作混合Δ-Σ/ SAR ADC（400）的积分器（30），以便产生等于第一电压（DeltaVbe）和第二电压（Vbe）之和的参考电压值（Vref）。 执行第一次积分以减小积分器输出电压摆幅。 如果比较器（22）耦合到积分器，则如果比较器不改变状态，则将第二电压（Vbe）积分在第一方向上。如果比较器（22）耦合到积分器，则将积分器的残差（Vresidue）乘以2.然后， 。 第一电压（DeltaVbe）集成在使积分器输出电压（Vout）等于2xVresidue-Vref或2xVresidue + Vref的方向上。
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4.发明申请Low-noise, wide offset range, programmable input offset amplifier front end and method 有权低噪声，宽偏移范围，可编程输入失调放大器前端和方法公开(公告)号：US20100019842A1
公开(公告)日：2010-01-28
申请号：US12229278
申请日：2008-08-21
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45197 , H03F3/45928 , H03F3/72 , H03F2203/45101 , H03F2203/45482 , H03F2203/45494 , H03F2203/45616 , H03F2203/45678 , H03F2203/45681
摘要： A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin−) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (−) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.
摘要翻译： 可编程偏移放大器包括具有与第一（Vin +）和第二（Vin-）输入电压耦合的差分连接的源极和第一（M1）和第二（M2）输入晶体管。 尾电流（Itail1）在第一和第二输入晶体管之间共享。 第一（M3）和第二（M4）负载装置分别耦合在参考电压和第一和第二输入晶体管的漏极之间。 输出级（13）具有耦合到第二输入晶体管的漏极的第一输入（+）和耦合到第一输入晶体管的漏极的第二输入（ - ）。 可编程电压变化在可编程输入偏移电路的输入元件上产生，以引起与输入晶体管的电极相关联的偏移电压的变化，其被反射回到放大器输入端以提供大的可编程输入参考偏移电压。
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公开(公告)号：US20090073011A1
公开(公告)日：2009-03-19
申请号：US11901355
申请日：2007-09-17
IPC分类号： H03M1/06
摘要： Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on measured gain error in a memory (44). The gain-adjusted LSB size is applied to the digital filter to cause gain-adjusted LSB size values to be added to or subtracted from accumulated content of the digital filter in accordance with a first or second state, respectively, of the comparator (30) during each cycle of the ADC. The final accumulated content after all required cycles of the ADC is a gain-corrected digital output signal (Dout(gain-corrected)).
摘要翻译： 通过将经增益调整的LSB大小基于测量的增益误差存储在存储器（44）中，在包括积分器（17），比较器（30）和数字滤波器（37）的ADC芯片中校正增益误差。 经增益调整的LSB大小被施加到数字滤波器，以使得根据比较器（30）的第一或第二状态，增加经调整的LSB大小值被添加到数字滤波器的累加内容或从累积内容中减去， 在ADC的每个周期。 ADC所需的所有周期之后的最终累加内容是增益校正的数字输出信号（Dout（增益校正））。
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6.发明申请Digital to analog converter architecture and method having low switch count and small output impedance 有权具有低开关数和小输出阻抗的数模转换器结构和方法公开(公告)号：US20080100489A1
公开(公告)日：2008-05-01
申请号：US11880568
申请日：2007-07-23
IPC分类号： H03M1/66
摘要： A digital to analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (V0) to produce coarse resolution node voltages (V0, . . . V240), and also includes a fine resolution resistor circuit (20) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D0,1 . . . ) to produce a first output voltage (Vout2), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Vout1), the second output voltage (Vout1) and the first output voltage (Vout2) providing a differential analog output signal (Vout1−Vout2). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R-2R networks.
摘要翻译： 数模转换器包括耦合在第一电压（Vin）和中间电压（V 0）之间的粗分辨率电阻电路（11），以产生粗分辨率节点电压（V 0，...，V 240），并且还包括 耦合在中间电压和第二电压（GND）之间的精细分辨率电阻电路（20）。 响应于数字输入（D 0,1 ...）的一组MSB位选择粗分辨率节点电压之一以产生第一输出电压（Vout 2），并且精细分辨率节点电压之一为 响应于数字输入的一组LSB位而选择以产生第二输出电压（Vout 1），第二输出电压（Vout 1）和第一输出电压（Vout 2）提供差分模拟输出信号（Vout 1 - Vout 2）。 在一个实施例中，粗分辨率和精细分辨率电阻电路是串电阻电路，在另一实施例中，它们是修改的R-2R网络。
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公开(公告)号：US08324881B2
公开(公告)日：2012-12-04
申请号：US12799288
申请日：2010-04-21
IPC分类号： G05F3/30
CPC分类号： G05F3/30 , H03F1/303 , H03F2200/447
摘要： A circuit for generating a band gap reference voltage (VREF) includes circuitry (I3×7) for supplying a first current to a first conductor (NODE1) and a second current to a second conductor (NODE2). The first conductor is successively coupled to a plurality of diodes (Q0×16), respectively, in response to a digital signal (CTL-VBE) to cause the first current to successively flow into selected diodes. The second conductor is coupled to collectors of the diodes which are not presently coupled to the first conductor. The diodes are successively coupled to the first conductor so that the first current causes the diodes, respectively, to produce relatively large VBE voltages on the first conductor and the second current causes sets of the diodes not coupled to the first conductor to produce relatively small VBE voltages on the second conductor. The relatively large and small VBE voltages provide differential band gap charges (QCA-QCB) which are averaged to provide a stable band gap reference voltage (VREF).
摘要翻译： 用于产生带隙参考电压（VREF）的电路包括用于向第一导体（NODE1）提供第一电流的电路（I3×7）和向第二导体（NODE2）提供第二电流的电路。 第一导体响应于数字信号（CTL-VBE）分别依次耦合到多个二极管（Q0×16），以使第一电流连续地流入选定的二极管。 第二导体耦合到当前不耦合到第一导体的二极管的集电极。 二极管连续地耦合到第一导体，使得第一电流分别导致二极管在第一导体上产生相对较大的VBE电压，并且第二电流使得未耦合到第一导体的二极管组产生相对较小的VBE 第二导体上的电压。 相对较大和较小的VBE电压提供差分带隙电荷（QCA-QCB），其被平均以提供稳定的带隙参考电压（VREF）。
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公开(公告)号：US20110260708A1
公开(公告)日：2011-10-27
申请号：US12799288
申请日：2010-04-21
IPC分类号： G05F3/16
CPC分类号： G05F3/30 , H03F1/303 , H03F2200/447
摘要： A circuit for generating a band gap reference voltage (VREF) includes circuitry (I3×7) for supplying a first current to a first conductor (NODE1) and a second current to a second conductor (NODE2). The first conductor is successively coupled to a plurality of diodes (Q0×16), respectively, in response to a digital signal (CTL-VBE) to cause the first current to successively flow into selected diodes. The second conductor is coupled to collectors of the diodes which are not presently coupled to the first conductor. The diodes are successively coupled to the first conductor so that the first current causes the diodes, respectively, to produce relatively large VBE voltages on the first conductor and the second current causes sets of the diodes not coupled to the first conductor to produce relatively small VBE voltages on the second conductor. The relatively large and small VBE voltages provide differential band gap charges (QCA-QCB) which are averaged to provide a stable band gap reference voltage (VREF).
摘要翻译： 用于产生带隙参考电压（VREF）的电路包括用于向第一导体（NODE1）提供第一电流的电路（I3×7）和向第二导体（NODE2）提供第二电流的电路。 第一导体响应于数字信号（CTL-VBE）分别依次耦合到多个二极管（Q0×16），以使第一电流连续地流入选定的二极管。 第二导体耦合到当前不耦合到第一导体的二极管的集电极。 二极管连续地耦合到第一导体，使得第一电流分别导致二极管在第一导体上产生相对较大的VBE电压，并且第二电流使得未耦合到第一导体的二极管组产生相对较小的VBE 第二导体上的电压。 相对较大和较小的VBE电压提供差分带隙电荷（QCA-QCB），其被平均以提供稳定的带隙参考电压（VREF）。
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9.发明授权Low-noise, wide offset range, programmable input offset amplifier front end and method 有权低噪声，宽偏移范围，可编程输入失调放大器前端和方法公开(公告)号：US07944287B2
公开(公告)日：2011-05-17
申请号：US12229278
申请日：2008-08-21
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45197 , H03F3/45928 , H03F3/72 , H03F2203/45101 , H03F2203/45482 , H03F2203/45494 , H03F2203/45616 , H03F2203/45678 , H03F2203/45681
摘要： A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin−) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (−) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.
摘要翻译： 可编程偏移放大器包括具有与第一（Vin +）和第二（Vin-）输入电压耦合的差分连接的源极和第一（M1）和第二（M2）输入晶体管。 尾电流（Itail1）在第一和第二输入晶体管之间共享。 第一（M3）和第二（M4）负载装置分别耦合在参考电压和第一和第二输入晶体管的漏极之间。 输出级（13）具有耦合到第二输入晶体管的漏极的第一输入（+）和耦合到第一输入晶体管的漏极的第二输入（ - ）。 可编程电压变化在可编程输入偏移电路的输入元件上产生，以引起与输入晶体管的电极相关联的偏移电压的变化，其被反射回到放大器输入端以提供大的可编程输入参考偏移电压。
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10.发明授权Low glitch offset correction circuit for auto-zero sensor amplifiers and method 有权用于自动调零传感器放大器和方法的低毛刺偏移校正电路公开(公告)号：US07605646B2
公开(公告)日：2009-10-20
申请号：US11890204
申请日：2007-08-03
IPC分类号： H03F1/02
CPC分类号： H03F3/45968 , H03F3/387 , H03F3/45475 , H03F2200/261 , H03F2203/45138 , H03F2203/45212
摘要： An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin−) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C). The fourth auto-zero stage is auto-zeroed to a the second voltage level, the second input signal is amplified by the third auto-zero stage, and the amplified second input signal is coupled to the output amplifier, during a fourth phase (D).
摘要翻译： 仪表放大器包括具有耦合到输出放大器（13）的输出（15A，B）的第一（11A）和第二（12A）输入放大器。 第一输入放大器中的第一自动归零级（20）被自动归零到第一电压电平（VREFL），第一输入信号（Vin +）被第一输入端的第二自动调零级（24）放大 放大器，并且放大的第一输入信号在第一阶段（A）期间耦合到输出放大器。 第二输入放大器中的第三自动调零级（44）自动归零至第二电压电平（VREFH），第二输入信号（Vin-）由第二自动调零级（40）放大，第二自动调零级 输入放大器，并且放大的第二输入信号在第二阶段（B）期间被耦合到输出放大器。 第二自动归零级自动归零到第一电压电平，第一输入信号由第一自动调零级（20）放大，放大的第一输入信号在第三阶段耦合到输出放大器 （C）。 第四自动调零级自动归零至第二电压电平，第二输入信号由第三自动调零级放大，放大后的第二输入信号在第四阶段（D ）。
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