公开(公告)号：US08694750B2

公开(公告)日：2014-04-08

申请号：US12339664

申请日：2008-12-19

申请人： Dmitry Vyshetsky ,  Paul Gyugyi

发明人： Dmitry Vyshetsky ,  Paul Gyugyi

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7211

摘要： Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.

摘要翻译： 本发明的实施例涉及一种用于允许在不改变应用固件的情况下在不同性能和成本的存储位置之间移动数据结构的方法和系统。 在一个实施例中，应用固件而不是应用固件直接访问存储器，应用程序固件通过参数来请求数据结构，实现返回指针。 参数可以是例如数据扇区的逻辑块地址，并且数据结构可以是该逻辑块地址（LBA）的映射和关联信息到闪存设备中的位置。

公开(公告)号：US20100161941A1

公开(公告)日：2010-06-24

申请号：US12340380

申请日：2008-12-19

申请人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

发明人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F13/1605 ,  G06F9/38

摘要： A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.

摘要翻译： 用于选择发出的闪速存储命令的子集以提高命令执行的处理时间的系统。 多个端口存储第一多个命令标识符并且与多个端口相关联。 第一多个仲裁器中的每一个在每个相应端口内的命令标识符之中选择最旧的命令标识符，导致第二多个命令标识符。 第二仲裁器基于命令标识符年龄和端口的优先级，从第二多个命令标识符中进行多个选择。 会话标识符队列存储与形成第三多个命令的其他命令中的与多个选择相关联的命令。 微控制器基于执行优化启发式方式从第三多个命令中选择可执行命令以执行。 执行该命令后，端口中的命令标识符被清除。

公开(公告)号：US20100161876A1

公开(公告)日：2010-06-24

申请号：US12339664

申请日：2008-12-19

申请人： Dmitry Vyshetsky ,  Paul Gyugyi

发明人： Dmitry Vyshetsky ,  Paul Gyugyi

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7211

摘要： Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.

摘要翻译： 本发明的实施例涉及一种用于允许在不改变应用固件的情况下在不同性能和成本的存储位置之间移动数据结构的方法和系统。 在一个实施例中，应用固件而不是应用固件直接访问存储器，应用程序固件通过参数来请求数据结构，实现返回指针。 参数可以是例如数据扇区的逻辑块地址，并且数据结构可以是该逻辑块地址（LBA）的映射和关联信息到闪存设备中的位置。

公开(公告)号：US09208108B2

公开(公告)日：2015-12-08

申请号：US12340380

申请日：2008-12-19

申请人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

发明人： Dmitry Vyshetsky ,  Howard Tsai ,  Paul Gyugyi

IPC分类号： G06F9/30 ,  G06F13/16 ,  G06F9/38

CPC分类号： G06F13/1605 ,  G06F9/38

摘要： A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.

摘要翻译： 用于选择发出的闪速存储命令的子集以提高命令执行的处理时间的系统。 多个端口存储第一多个命令标识符并且与多个端口相关联。 第一多个仲裁器中的每一个在每个相应端口内的命令标识符之中选择最旧的命令标识符，导致第二多个命令标识符。 第二仲裁器基于命令标识符年龄和端口的优先级，从第二多个命令标识符中进行多个选择。 会话标识符队列存储与形成第三多个命令的其他命令中的与多个选择相关联的命令。 微控制器基于执行优化启发式方式从第三多个命令中选择可执行命令以执行。 执行该命令后，端口中的命令标识符被清除。

公开(公告)号：US08683293B2

公开(公告)日：2014-03-25

申请号：US12639850

申请日：2009-12-16

申请人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Paul Gyugyi

发明人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Paul Gyugyi

IPC分类号： H03M13/00

CPC分类号： H03M13/152 ,  H03M13/1575

摘要： An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.

摘要翻译： 用于纠正两位错误的错误定位器单元。 误差定位器单元包括多个操作单元，归一化基变换单元和转换单元。 多个操作单元基于伽罗瓦域的第一个基于所生成的校正子来计算多项式的系数。 对系数进行操作会在第一个基础上产生根定义值向量。 归一化基变换单元将根定义值向量变换为正常基，以产生多个根。 转换单元将多个根转换为第一基。 基于系数计算的缩放因子被应用于转换单元的输出，以在第一基础上产生用于所述多项式的多个缩放根。 添加多个缩放根以产生多项式的误差位置。

公开(公告)号：US20110145677A1

公开(公告)日：2011-06-16

申请号：US12639850

申请日：2009-12-16

申请人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Paul Gyugyi

发明人： Nirmal Saxena ,  Howard Tsai ,  Dmitry Vyshetsky ,  Paul Gyugyi

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/152 ,  H03M13/1575

摘要： An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.

摘要翻译： 用于纠正两位错误的错误定位器单元。 误差定位器单元包括多个操作单元，归一化基变换单元和转换单元。 多个操作单元基于伽罗瓦域的第一个基于所生成的校正子来计算多项式的系数。 对系数进行操作会在第一个基础上产生根定义值向量。 归一化基变换单元将根定义值向量变换为正常基，以产生多个根。 转换单元将多个根转换为第一基。 基于系数计算的缩放因子被应用于转换单元的输出，以在第一基础上产生用于所述多项式的多个缩放根。 添加多个缩放根以产生多项式的误差位置。

公开(公告)号：US09110714B2

公开(公告)日：2015-08-18

申请号：US12504313

申请日：2009-07-16

申请人： Alexander Joffe ,  Dmitry Vyshetsky

发明人： Alexander Joffe ,  Dmitry Vyshetsky

IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F9/48 ,  G06F9/38 ,  G06F9/52

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/52 ,  G06F2209/507

摘要： In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

公开(公告)号：US20090150689A1

公开(公告)日：2009-06-11

申请号：US12342865

申请日：2008-12-23

申请人： Brad W. Simeral ,  David C. Reed ,  Dmitry Vyshetsky ,  Roman Surgutchick ,  Robert William Chapman ,  Joshua Titus ,  Anand Srinivasan ,  Hari U. Krishnan

发明人： Brad W. Simeral ,  David C. Reed ,  Dmitry Vyshetsky ,  Roman Surgutchick ,  Robert William Chapman ,  Joshua Titus ,  Anand Srinivasan ,  Hari U. Krishnan

IPC分类号： G06F1/32

CPC分类号： G06F1/28 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component. It also includes a controller for adjusting operational characteristics of the component for modifying the power consumed by the component to comply with a performance profile, which generally specifies permissible power consumption levels for the component.

摘要翻译： 公开了一种数据路径控制器，计算机设备，装置和方法，用于将电源管理功能集成到数据路径控制器中，以管理由处理器和外围设备消耗的功率。 通过在数据路径控制器内部嵌入电源管理，数据路径控制器可以有利地在现场修改其标准，使得其能够根据处理器和外围设备的变化来适应其功率管理动作。 此外，数据路径控制器包括功率管理接口，其提供用于监视和/或量化各种组件的功耗的功率监控端口。 在一个实施例中，数据路径控制器包括用于可选地监视组件的功率的功率监视接口。 它还包括用于调整部件的操作特性的控制器，用于修改部件消耗的功率以符合性能曲线，其通常指定部件的允许功率消耗水平。

公开(公告)号：US06330584B1

公开(公告)日：2001-12-11

申请号：US09055033

申请日：1998-04-03

申请人： Alexander Joffe ,  Dmitry Vyshetsky

发明人： Alexander Joffe ,  Dmitry Vyshetsky

IPC分类号： G06F900

CPC分类号： G06F9/5011 ,  G06F9/3851 ,  G06F9/462 ,  G06F9/4881 ,  G06F2209/507

摘要： In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

摘要翻译： 在多任务流水线处理器中，连续的指令由不同的任务执行，消除了当前一条指令无法完成时清除随后指令的指令执行流水线的需要。 任务不共享存储任务特定值的寄存器，因此在新任务计划执行时不需要保存或加载寄存器。 如果指令访问不可用资源，则指令将被暂停，从而允许执行其他任务的指令，直到资源变为可用。 任务调度由硬件执行; 不需要操作系统。 提供简单的技术来同步不同任务之间的共享资源访问。

公开(公告)号：US09465728B2

公开(公告)日：2016-10-11

申请号：US12939135

申请日：2010-11-03

申请人： Howard Tsai ,  Dmitry Vyshetsky ,  Neal Meininger

发明人： Howard Tsai ,  Dmitry Vyshetsky ,  Neal Meininger

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F13/16

CPC分类号： G06F12/02 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1689 ,  G06F13/1694

摘要： A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.

摘要翻译： 在一个实施例中，存储器控制器包括命令转换数据结构，前端和后端。 命令翻译数据结构将命令操作映射到原语，其中原语从为一个或多个存储器件确定的命令操作中分解。 前端从处理单元接收命令操作，并且使用命令翻译数据结构将每个命令操作转换成一组一个或多个相应的原语。 后端将针对每个接收到的命令操作的一个或多个相应基元的集合输出到给定的存储器件。