公开(公告)号：US5506734A

公开(公告)日：1996-04-09

申请号：US99611

申请日：1993-07-30

申请人： Marco M. Monti ,  Andrea Onetti ,  Domenico Rossi

发明人： Marco M. Monti ,  Andrea Onetti ,  Domenico Rossi

IPC分类号： G11B20/02 ,  G11B5/027 ,  G11B15/02 ,  G11B15/12 ,  G11B15/18 ,  G11B5/09

CPC分类号： G11B15/026 ,  G11B15/125 ,  G11B15/18

摘要： A drive circuit having two electronic switches formed from N-MOS transistors is designed to alternatively connect the input of a preamplifier stage to a first or second read sensor on the read head of a magnetic tape. The drive circuit also has a third electronic switch formed from an N-MOS transistor which grounds the input of the preamplifier stage. Based on logic input signals, a control circuit switches the first and second switches, or closes the third switch and simultaneously opens the first and second switches.

摘要翻译： 具有由N-MOS晶体管形成的两个电子开关的驱动电路设计成将前置放大器级的输入交替地连接到磁带的读取磁头上的第一或第二读取传感器。 驱动电路还具有由N-MOS晶体管形成的第三个电子开关，其将前置放大器级的输入接地。 基于逻辑输入信号，控制电路切换第一和第二开关，或者关闭第三开关并同时打开第一和第二开关。

公开(公告)号：US5241226A

公开(公告)日：1993-08-31

申请号：US805494

申请日：1991-12-11

申请人： Domenico Rossi ,  Andrea Onetti ,  Marco M. Monti

发明人： Domenico Rossi ,  Andrea Onetti ,  Marco M. Monti

IPC分类号： H03F1/00 ,  H03F1/30 ,  H03F3/181 ,  H03F3/72

CPC分类号： H03F3/72 ,  H03F1/303

摘要： A circuit for suppressing the noise produced by the switching of two voltage sources having a direct current offset and connected alternately to the input of an amplification stage. The circuit comprises a low-pass filter between the two voltage sources and the amplification stage, which filter is normally disabled during normal operation of the amplification stage, and is only enabled during switching of the two voltage sources, so as to enable a gradual change in the direct voltage supplied to the input of the amplification stage and due to the offset between the two sources.

公开(公告)号：US5483189A

公开(公告)日：1996-01-09

申请号：US332831

申请日：1994-10-31

申请人： Paolo Cordini ,  Giorgio Pedrazzini ,  Domenico Rossi

发明人： Paolo Cordini ,  Giorgio Pedrazzini ,  Domenico Rossi

IPC分类号： H03K19/0175 ,  H03K5/153

CPC分类号： H03K19/017563 ,  H03K19/01759

摘要： A stage of both input and output configurable for operation with low and high voltages, comprises:first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means;at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); andan input circuit (3) having a first input terminal connected to the circuit node (A), a second input terminal connected to a reference voltage (Vref3), and at least one output terminal forming an output terminal of the stage (I).

摘要翻译： 输入和输出可配置为用于低电压和高电压操作的阶段包括：第一（M1），第二（M2）和第三（M3）晶体管，每个具有第一和第二端子以及控制端子，第一和第二端子 和第一晶体管（M1）的控制端子分别连接到电压源的第一端子，第二晶体管（M2）的第一端子和驱动电路装置，第二晶体管的第二端子和控制端子 M2）分别连接到电路节点（A），形成载物台（1）的输入/输出端子，分别连接到驱动电路装置，第三晶体管（M3）的第一和第二端子和控制端子分别 连接到电压源的第二端子，电路节点（A）和驱动电路装置; 连接在第二晶体管（M2）的第一和第二端子之间的至少一个二极管（D2）; 以及输入电路（3），其具有连接到所述电路节点（A）的第一输入端子，连接到参考电压（Vref3）的第二输入端子和形成所述载物台（I）的输出端子的至少一个输出端子， 。

公开(公告)号：US4928049A

公开(公告)日：1990-05-22

申请号：US245657

申请日：1988-09-16

申请人： Giovanni Pietrobon ,  Domenico Rossi ,  Salvatore Pappalardo

发明人： Giovanni Pietrobon ,  Domenico Rossi ,  Salvatore Pappalardo

IPC分类号： H02P8/12

CPC分类号： H02P8/12

摘要： The circuit controls current switching in multiple inductive loads (L1, L2, L3, L4) fed by means of respective switching switches (SW1, SW2, SW3, SW4) and by means of respective current adjustment switches (SWA, SWB), and comprises a single sense resistor (R) in series to said switching switches, and a single comparator circuit (C, FF) adapted to generate a logical signal (Q) when the voltage across the sense resistor exceeds a reference voltage (V.sub.ref), which drives a plurality of AND gates (PA, PB) which control said adjustment switches and the second inputs whereof are driven by respective square-wave signals in opposite phase with a period equal to twice the switching period.

公开(公告)号：US5629610A

公开(公告)日：1997-05-13

申请号：US436947

申请日：1995-05-08

申请人： Giorgio Pedrazzini ,  Giuseppe Scrocchi ,  Paolo Cordini ,  Domenico Rossi

发明人： Giorgio Pedrazzini ,  Giuseppe Scrocchi ,  Paolo Cordini ,  Domenico Rossi

IPC分类号： G05F1/56 ,  H02M1/08 ,  H02M3/155 ,  H02M3/156 ,  G05F1/563

CPC分类号： H02M3/156 ,  H02M3/1563

摘要： A fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance. The first comparator exerts an open-loop current mode control. The second comparator, establishing a second higher current threshold than the current threshold set by the first comparator, triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator. The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.

摘要翻译： 全数字电流模式通过采用两个不同的比较器来实现PWM控制，这两个比较器都读取感测电阻上的电压降。 第一个比较器进行开环电流模式控制。 第二比较器建立比由第一比较器设置的电流阈值更高的第二高电流阈值，在通过输出级的电流电平不可控地超过第二阈值时，触发输出功率晶体管的禁用电路达预设时间段 。 这可能是因为在第一（开环控制）比较器的开关延迟时段期间存储的额外能量的输出功率晶体管的非相位期间来自负载电路电感的不充分的放电。 突发序列的频率可以被精确地控制在很好的在感兴趣的频率范围之外，以防止干扰。

公开(公告)号：US5150073A

公开(公告)日：1992-09-22

申请号：US628023

申请日：1990-12-17

申请人： Bruno Murari ,  Domenico Rossi ,  Pierantonio Savino

发明人： Bruno Murari ,  Domenico Rossi ,  Pierantonio Savino

IPC分类号： G11B5/027 ,  G11B5/02 ,  H03F3/181 ,  H03F3/343 ,  H03F3/45

CPC分类号： G11B5/02 ,  H03F3/343 ,  H03F3/45479

摘要： A low-noise preamplifier stage, in particular for magnetic heads, which comprises an input stage comprising a differential circuit and a single-transistor output stage, wherein the differential stage has an intrinsic offset voltage, is ground-connectable and can be directly coupled to the magnetic head, the two transistors forming the differential circuit having different bias currents in order to reduce the input equivalent noise, the base terminal of the first transistor of the differential circuit defining an input of the stage which can be connected directly to a terminal of the magnetic head, the other terminal of the head being connected directly to the ground, the base terminal of the other transistor of the different circuit being connected to the intermediate point of a pair of resistors which are mutually connected in series between the single transistor of the output stage and a line at reference voltage, so that the differential stage biases the output with its offset voltage without requiring additional components for this purpose.

公开(公告)号：US4980576A

公开(公告)日：1990-12-25

申请号：US364172

申请日：1989-06-12

申请人： Domenico Rossi ,  Claudio Diazzi

发明人： Domenico Rossi ,  Claudio Diazzi

IPC分类号： H02M3/07 ,  H02M3/155 ,  H02M3/156 ,  H02M7/538 ,  H03K17/06 ,  H03K17/082 ,  H03K17/60

CPC分类号： H03K17/0826 ,  H02M3/156 ,  H02M7/538 ,  H03K17/063

摘要： The circuit comprises a tank capacitance and a charge circuit supplied with the same voltage as the bridge and comprising an inductance and a control transistor. There is also provided a control circuit, which comprises an oscillator controlling the periodic switching of control transistor and a comparator which controls the momentary clamping of control transistor in the condition wherein the charge circuit is interrupted when the difference between the voltage across capacitance and the power supply voltage exceeds a preset maximum value and the unclamping of the same transistor when such difference falls below a preset minimum value. A further comparator similarly clamps control transistor if there is an excess current in the transistor itself.

公开(公告)号：US4950919A

公开(公告)日：1990-08-21

申请号：US194602

申请日：1988-05-16

申请人： Domenico Rossi ,  Claudio Diazzi ,  Carlo Cini

发明人： Domenico Rossi ,  Claudio Diazzi ,  Carlo Cini

IPC分类号： H02P7/00 ,  H03K17/687 ,  H03K17/695

CPC分类号： H03K17/6871 ,  H02P7/04

摘要： In this MOS-transistor bridge circuit, for obtaining a fast flyback conduction of the current after a normal operation of the circuit, instead of the flyback diodes associated with each transistor of the bridge, the MOS transistors themselves are employed, driven so as to conduct current from the ground to the power supply, that is in the opposite direction with respect to that of normal operation. For this purpose a control section is provided receiving at the input a fast flyback signal and comprising delay gates connected to the disable inputs of the transistors, so as to delay switching off thereof, and to maintain in the on state two diagonally opposed transistors so as to allow current to flow from the ground to the power supply through these diagonally opposed transistors and the load until the current decreases to zero.

公开(公告)号：US4879641A

公开(公告)日：1989-11-07

申请号：US263935

申请日：1988-10-28

申请人： Domenico Rossi ,  Andrea Cuomo

发明人： Domenico Rossi ,  Andrea Cuomo

IPC分类号： H02M7/5387 ,  H02P7/00

CPC分类号： H02M7/53871 ,  H02P7/04 ,  H02M2003/1555

摘要： A circuit for sensing the magnitude and sense of a current flowing through the load of an H-bridge stage driving the load in a switching mode by means of a clocked, square-wave driving signal and the inverted signal thereof applied, respectively, to two pairs of analog switches arranged in a bridge configuration and functionally switching the load between a supply node and a virtual ground node is made by utilizing a single sensing resistance connected between the virtual ground node and the real ground node of the circuit, the signal across the resistance and the inverted signal thereof are fed to two inputs of an analog multiplex whose output signal is fed to the input of a comparator in order to obtain at the output of the latter a signal with an amplitude proportional to the intensity of the current and a polarity determined by the polarity of a reference voltage which is applied to another input of the comparator. The PWM control loop may then be completed by means of a flip-flop to the inputs of which the output signal of the comparator and a clock signal are applicable in order to generate at the output of the flip-flop the clocked driving signal.

摘要翻译： 一种电路，用于感测流过H桥级的负载的电流的大小和感测，该H电桥级通过时钟方波驱动信号及其反相信号分别以切换模式驱动负载，分别施加到两个 通过利用连接在电路的虚拟接地节点和实际接地节点之间的单个感测电阻来实现布置成桥式配置并且功能地切换供电节点和虚拟接地节点之间的负载的模拟开关对， 电阻及其反相信号被馈送到模拟多路复用的两个输入，其输出信号被馈送到比较器的输入端，以便在其输出端获得具有与电流的强度成正比的信号和 极性由施加到比较器的另一个输入的参考电压的极性决定。 然后可以通过触发器将PWM控制环路完成到其比较器的输出信号和时钟信号的输入端，以在触发器的输出端产生时钟驱动信号。

公开(公告)号：US06271567B1

公开(公告)日：2001-08-07

申请号：US09227946

申请日：1999-01-11

申请人： Massimo Pozzoni ,  Paolo Cordini ,  Domenico Rossi ,  Giorgio Pedrazzini ,  Paola Galbiati ,  Michele Palmieri ,  Luca Bertolini

发明人： Massimo Pozzoni ,  Paolo Cordini ,  Domenico Rossi ,  Giorgio Pedrazzini ,  Paola Galbiati ,  Michele Palmieri ,  Luca Bertolini

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.

摘要翻译： 在包括功率DMOS晶体管的结隔离集成电路中，形成在相应的阱区域中或者在相反导电类型的衬底上的隔离的外延区域中形成的电路形成在对供过剩和/或地下效应敏感的不同隔离区域中。 这些影响是由耦合到电源轨或地的各个功率DMOS晶体管引起的。 这些效果可以通过特定形状的布置布置来替代地控制，并且可以被有效地保护免受两种影响。 这通过介于敏感电路的区域和包含不形成替代可实施的电路布置的功率DMOS晶体管的区域来实现，该区域包含耦合到电源轨的功率DMOS晶体管或接地导轨， 可替代地实施的布置形成。 特殊插件将灵敏电路与供电或地下效应不受特定电路布置的电源设备分离和屏蔽。