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20 条记录 (耗时 0.023 秒)

    Belowground and oversupply protection of junction isolated integrated circuits
    1.
    发明授权
    Belowground and oversupply protection of junction isolated integrated circuits 有权
    接地隔离集成电路的地下和过充保护

    公开(公告)号：US06271567B1

    公开(公告)日：2001-08-07

    申请号：US09227946

    申请日：1999-01-11

    申请人： Massimo Pozzoni ,  Paolo Cordini ,  Domenico Rossi ,  Giorgio Pedrazzini ,  Paola Galbiati ,  Michele Palmieri ,  Luca Bertolini

    发明人： Massimo Pozzoni ,  Paolo Cordini ,  Domenico Rossi ,  Giorgio Pedrazzini ,  Paola Galbiati ,  Michele Palmieri ,  Luca Bertolini

    IPC分类号： H01L2362

    CPC分类号： H01L27/0266

    摘要： In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.

    摘要翻译： 在包括功率DMOS晶体管的结隔离集成电路中，形成在相应的阱区域中或者在相反导电类型的衬底上的隔离的外延区域中形成的电路形成在对供过剩和/或地下效应敏感的不同隔离区域中。 这些影响是由耦合到电源轨或地的各个功率DMOS晶体管引起的。 这些效果可以通过特定形状的布置布置来替代地控制，并且可以被有效地保护免受两种影响。 这通过介于敏感电路的区域和包含不形成替代可实施的电路布置的功率DMOS晶体管的区域来实现，该区域包含耦合到电源轨的功率DMOS晶体管或接地导轨， 可替代地实施的布置形成。 特殊插件将灵敏电路与供电或地下效应不受特定电路布置的电源设备分离和屏蔽。

    Process for the fabrication of semiconductor devices having various buried regions
    3.
    发明授权
    Process for the fabrication of semiconductor devices having various buried regions 失效
    具有各种埋置区域的半导体器件的制造方法

    公开(公告)号：US5789288A

    公开(公告)日：1998-08-04

    申请号：US854584

    申请日：1997-05-12

    申请人： Michele Palmieri ,  Paola Galbiati ,  Lodovica Vecchi

    发明人： Michele Palmieri ,  Paola Galbiati ,  Lodovica Vecchi

    IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L21/8249

    CPC分类号： H01L21/266 ,  H01L21/74 ,  H01L21/8249

    摘要： A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it. The process described allows the production of integrated devices with an additional buried layer while utilizing one fewer mask than conventional processes.

    摘要翻译： 一种用于通过形成氮化硅层（52）来掺杂P型衬底（50）的方法，通过该层注入N型杂质（图7），形成抗蚀剂掩模（54），其离开至少一个区域 （图8），包含暴露的氮化物层的一部分，首先用不足的能量注入N型杂质，然后以足够的能量穿过氮化物层，使衬底（图9）高 在氧化环境中进行温度处理以在未被氮化物层覆盖的衬底的区域上形成二氧化硅焊盘（55），去除氮化物层并且将P型杂质注入到由衬垫限定的区域中。 然后，该过程继续移除焊盘，并且以常规方式，形成外延层并选择性地掺杂以在其中形成P型和N型区域。 所描述的方法允许使用附加掩埋层的集成器件的生产，同时使用比常规工艺少的掩模。

    VDMOS transistor with improved breakdown characteristics
    5.
    发明授权
    VDMOS transistor with improved breakdown characteristics 失效
    VDMOS晶体管具有改进的击穿特性

    公开(公告)号：US5430316A

    公开(公告)日：1995-07-04

    申请号：US19124

    申请日：1993-02-17

    申请人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

    发明人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

    IPC分类号： H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68

    CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7813 ,  Y10S148/053 ,  Y10S148/126

    摘要： The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.

    摘要翻译： VDMOS晶体管的击穿电压显着增加，而不会通过将源极单元阵列与漏极扩散分离的场氧化物条带的边缘部分下方形成的场隔离扩散电位相扣合来抑制器件的其它电气特性 ，到晶体管的源极电位。 这可以通过将外围源电池的体区域延伸到每隔给定数量的外围电池单元面向磁场隔离结构条带直到其与所述场隔离扩散相交的方式来实现。 通过这样连接每个给定数量的单元的一个外围源单元，集成晶体管的总体通道宽度的实际减小可以忽略不计，从而保留功率晶体管的电气特性。

    Integrated N-channel power MOS bridge circuit
    6.
    发明授权
    Integrated N-channel power MOS bridge circuit 失效
    集成N沟道功率MOS桥接电路

    公开(公告)号：US4949142A

    公开(公告)日：1990-08-14

    申请号：US773316

    申请日：1985-09-06

    申请人： Claudio Contiero ,  Paola Galbiati

    发明人： Claudio Contiero ,  Paola Galbiati

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78

    CPC分类号： H01L27/088

    摘要： The disclosed bridge circuit is fabricated using power MOS technology. Common terminals of the bridge circuit are integrated into common regions in the implementation. Electrodes, typically coupled together in the bridge circuit, are implemented by a shared conducting region in the integrated circuit of the semiconductor chip. By integrating the elements of the circuit, less area of the semiconductor chip is required as compared to an implementation involving 4 (four) discrete elements. Diodes are fabricated across the transistors to protect the elements against reverse biasing.

    摘要翻译： 所公开的桥式电路使用功率MOS技术制造。 桥接电路的公共端子在实现中被集成到公共区域中。 通常在桥式电路中耦合在一起的电极由半导体芯片的集成电路中的共用导电区域实现。 通过集成电路的元件，与涉及4（4）个分立元件的实现相比，需要较少的半导体芯片面积。 二极管跨越晶体管制造，以保护元件免受反向偏置。

    Mixed technology integrated circuit comprising CMOS structures and efficient lateral bipolar transistors with a high early voltage and fabrication thereof
    8.
    发明授权
    Mixed technology integrated circuit comprising CMOS structures and efficient lateral bipolar transistors with a high early voltage and fabrication thereof 失效
    包括CMOS结构的混合技术集成电路和具有高的早期电压和其制造的高效侧向双极晶体管

    公开(公告)号：US5081517A

    公开(公告)日：1992-01-14

    申请号：US548711

    申请日：1990-07-06

    申请人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

    发明人： Claudio Contiero ,  Paola Galbiati ,  Lucia Zullino

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

    CPC分类号： H01L27/0623 ,  H01L21/8249

    摘要： A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CDES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.

    摘要翻译： 高密度，混合技术的集成电路包括CMOS结构和双极横向晶体管，通过在收集器区域形成“阱”区域，电效率和早期电压保持较高。 该操作确定在外延层内形成相对较深的“集电极延伸区域”，以便截取发射极电流并将其收集到集电极，并将其从色散向衬底通过围绕着该区域的相邻隔离结 横向双极晶体管。 在可比较的条件下，IcI衬底之间的比例从大约8增加到大约300，而早期电压从大约20V增加到大约100V。 VCEO，BVCBO和BVCDES电压也有利地通过在收集器区域中形成的所述“阱”区域的存在来增加。

    Semiconductor diode integrated with bipolar/CMOS/DMOS technology
    10.
    发明授权
    Semiconductor diode integrated with bipolar/CMOS/DMOS technology 失效
    集成了双极/ CMOS / DMOS技术的半导体二极管

    公开(公告)号：US5629558A

    公开(公告)日：1997-05-13

    申请号：US454647

    申请日：1995-05-31

    申请人： Paola Galbiati ,  Ubaldo Mastromatteo

    发明人： Paola Galbiati ,  Ubaldo Mastromatteo

    IPC分类号： H01L21/329 ,  H01L29/861 ,  H01L27/06 ,  H01L29/00 ,  H01L31/0352

    CPC分类号： H01L29/66128 ,  H01L29/8611

    摘要： A diode integrated on semiconductor material with BCD technology and of the type provided on a substrate having a first type of conductivity inside an isolation region having a second type of conductivity. The diode comprises also a buried anode region having a first type of conductivity and a cathode region having a second type of conductivity. The cathode region comprises an epitaxial layer located above the buried anode region and a highly doped region provided inside the epitaxial layer. The buried anode region comprises depressions opposite which is located the highly doped region with the depressions being achieved by the intersection of lateral diffusions of distinct and adjacent portions of the buried anode region.

    摘要翻译： 集成在具有BCD技术的半导体材料上的二极管，并且具有在具有第二类导电性的隔离区域内具有第一类型导电性的基板上提供的类型的二极管。 二极管还包括具有第一类导电性的掩埋阳极区域和具有第二类导电性的阴极区域。 阴极区域包括位于掩埋阳极区域上方的外延层和设置在外延层内部的高掺杂区域。 掩埋阳极区域包括相对的凹陷，其位于高掺杂区域，凹陷通过掩埋阳极区域的不同相邻部分的横向扩散的交叉来实现。