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    Parallel integrated circuit having DSP module and CPU core operable for switching between two independent asynchronous clock sources while the system continues executing instructions
    1.
    发明授权
    Parallel integrated circuit having DSP module and CPU core operable for switching between two independent asynchronous clock sources while the system continues executing instructions 失效
    具有DSP模块和CPU核的并行集成电路可操作用于在系统继续执行指令时在两个独立的异步时钟源之间切换

    公开(公告)号：US5603017A

    公开(公告)日：1997-02-11

    申请号：US309546

    申请日：1994-09-20

    申请人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

    发明人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F1/04

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

    摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

    Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of different frequencies while the CPU continues executing instructions
    4.
    发明授权
    Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of different frequencies while the CPU continues executing instructions 失效
    具有CPU核心的集成电路可操作用于在CPU继续执行指令时在不同频率的两个独立异步时钟源之间切换

    公开(公告)号：US5872960A

    公开(公告)日：1999-02-16

    申请号：US624879

    申请日：1996-03-27

    申请人： Oved Oz ,  Gideon Intrater ,  Yachin Afek

    发明人： Oved Oz ,  Gideon Intrater ,  Yachin Afek

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F1/04

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

    摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

    Integrated data processing system utilizing successive approximation analog to digital conversion and PWM for parallel disconnect
    5.
    发明授权
    Integrated data processing system utilizing successive approximation analog to digital conversion and PWM for parallel disconnect 失效
    采用逐次逼近模数转换和PWM并联断开的集成数据处理系统

    公开(公告)号：US5613149A

    公开(公告)日：1997-03-18

    申请号：US546187

    申请日：1995-10-20

    申请人： Yachin Afek ,  Oved Oz ,  Gideon Intrater

    发明人： Yachin Afek ,  Oved Oz ,  Gideon Intrater

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F11/00 ,  G06F15/16

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： An integrated circuit structure for use in identifying a value of an analog signal includes a central processing unit that executes instructions to perform data processing operations. The data processing operations include a successive approximation analog-to-dialog conversion operation to provide a digital value based upon an input data signal. A pulse with modulation (PWM) element converts the digital value to a square-wave output signal having a duty cycle corresponding to the digital value. A PWM element is adapted for connection to a low pass filter such that the square-wave output signal is provided as an input to the low pass filter. The low pass filter provides an output analog signal corresponding to the duty cycle of the square-wave output signal. An input port is adapted for connection to an output of a comparator. The comparator receives as inputs the output analog signal the low pass filter and the analog signal. The input port is connected to provide the output of the comparator as the input data signal to the central processing unit.

    摘要翻译： 用于识别模拟信号的值的集成电路结构包括执行指令以执行数据处理操作的中央处理单元。 数据处理操作包括逐次近似模拟对话转换操作，以基于输入数据信号提供数字值。 具有调制（PWM）元件的脉冲将数字值转换成具有对应于数字值的占空比的方波输出信号。 PWM元件适于连接到低通滤波器，使得方波输出信号被提供为低通滤波器的输入。 低通滤波器提供与方波输出信号的占空比对应的输出模拟信号。 输入端口适于连接到比较器的输出。 比较器接收低通滤波器和模拟信号的输出模拟信号作为输入。 连接输入端口，将比较器的输出作为输入数据信号提供给中央处理单元。

    Integrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnect
    6.
    发明授权
    Integrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnect 失效
    具有CPU内核和并行独立运行的DSP模块的集成数据处理系统，利用逐次逼近模数和PWM并行断开

    公开(公告)号：US5491828A

    公开(公告)日：1996-02-13

    申请号：US307399

    申请日：1994-09-16

    申请人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

    发明人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F11/00 ,  G06F15/16

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

    摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

    GHZ range frequency divider in CMOS
    7.
    发明授权
    GHZ range frequency divider in CMOS 失效
    GHZ范围分频器在CMOS

    公开(公告)号：US5907589A

    公开(公告)日：1999-05-25

    申请号：US838592

    申请日：1997-04-10

    申请人： Vladimir Koifman ,  Yachin Afek

    发明人： Vladimir Koifman ,  Yachin Afek

    IPC分类号： H03K3/356 ,  H03K21/00

    CPC分类号： H03K3/356113

    摘要： A frequency divider (50) comprises complementary components (e.g., CMOS transistors) which are placed in two complementary portions (10, 20) with similar structures. The portions are coupled by four lines (131-134). Each line (e.g., 131) is coupled to a pair of transistors including a pull device (e.g., 271) and a hold device (e.g., 291). The devices receives identical signals from another line (e.g., 134) and the input signal X in the same, non-inverted form. The devices have complementary logical functions because of their complementary structures (serial.backslash.parallel) and complementary components (P-FET, N-FET). When a line (e.g., 131) is pulled to a reference line (e.g., 91), contention between the devices is substantially avoided. There is no need to provide the input signal X in a non-inverted and in an inverted form.

    摘要翻译： 分频器（50）包括互补部件（例如，CMOS晶体管），其被放置在具有相似结构的两个互补部分（10,20）中。 这些部分连接四行（131-134）。 每一行（例如，131）耦合到一对晶体管，其包括拉设备（例如271）和保持装置（例如，291）。 这些装置以相同的非反相形式从另一条线（例如，134）和输入信号X接收相同的信号。 这些器件具有互补的逻辑功能，因为它们的互补结构（串行+ 544并行）和互补组件（P-FET，N-FET）。 当线（例如131）被拉到参考线（例如，91）时，基本上避免了装置之间的争用。 不需要以非反相和倒置形式提供输入信号X.

    Fast start-up circuit
    8.
    发明授权
    Fast start-up circuit 失效
    快速启动电路

    公开(公告)号：US5892381A

    公开(公告)日：1999-04-06

    申请号：US868335

    申请日：1997-06-03

    申请人： Vladimir Koifman ,  Yachin Afek ,  Eliezer Sand ,  Kiyoshi Kase

    发明人： Vladimir Koifman ,  Yachin Afek ,  Eliezer Sand ,  Kiyoshi Kase

    IPC分类号： H03F1/00 ,  G05F1/46 ,  G05F3/16

    CPC分类号： G05F1/468

    摘要： The rise time of a voltage Vo presented to a load, based on an input voltage Vi provided via an RC filter coupled to the load for removing higher frequency noise on Vo, is substantially reduced by providing a sensor circuit with differential inputs Vi, Vo. The sensor circuit drives a charger circuit coupled to a DC potential and the load so that rapid charging of C to Vo does not depend on R. As Vo approaches Vi, the sensor circuit deactivates the charger circuit to stop further charging and a latch coupled to the sensor circuit shuts off the sensor circuit to reduce power consumption while (Vo.about.Vi)>0. A current mirror buffer is desirably included between the sensor output and the latch for level shifting.

    摘要翻译： 基于通过耦合到负载的用于消除Vo上的更高频率噪声的RC滤波器提供的输入电压Vi，提供给负载的电压Vo的上升时间通过向具有差分输入Vi，Vo的传感器电路提供而大大减少。 传感器电路驱动耦合到直流电位和负载的充电器电路，使得C至Vo的快速充电不依赖于R.当Vo接近Vi时，传感器电路使充电器电路停用以停止进一步的充电，并将锁存器耦合到 传感器电路关闭传感器电路，以减少功耗（Vo差分Vi）> 0。 理想地，传感器输出和锁存器之间包括电流镜缓冲器以进行电平转换。

    Low voltage class AB amplifier
    9.
    发明授权
    Low voltage class AB amplifier 失效
    低电压AB类放大器

    公开(公告)号：US5825246A

    公开(公告)日：1998-10-20

    申请号：US699255

    申请日：1996-08-19

    申请人： Vladimir Koifman ,  Yachin Afek ,  Israel Kashat

    发明人： Vladimir Koifman ,  Yachin Afek ,  Israel Kashat

    IPC分类号： H03F3/30 ,  H03F3/45

    CPC分类号： H03F3/45192 ,  H03F3/3001

    摘要： The amplifier (200) includes an input stage (220) coupled to two output transistors (281, 282) having a common terminal at the output terminal (206) of the amplifier. Class AB operation of the output transistors (281, 282) is possible at a comparatively low supply voltage. In order to obtain such operation, measurement transistors (271, 272) are coupled to the same control input (283, 284) as the output transistors (281, 282). These measurement transistors (271, 272) are serially coupled to a current mirror (260). The quiescent current of the output transistors (281, 282) is measured and used to produce a feedback signal which is superimposed to the control signals.

    摘要翻译： 放大器（200）包括耦合到在放大器的输出端（206）处具有公共端的两个输出晶体管（281,282）的输入级（220）。 在相对低的电源电压下，输出晶体管（281,282）的AB类操作是可能的。 为了获得这样的操作，测量晶体管（271,272）耦合到与输出晶体管（281,282）相同的控制输入（283,284）。 这些测量晶体管（271,272）串联耦合到电流镜（260）。 输出晶体管（281,282）的静态电流被测量并用于产生叠加到控制信号的反馈信号。

    Differential switched capacitor circuit
    10.
    发明授权
    Differential switched capacitor circuit 失效
    差分开关电容电路

    公开(公告)号：US5514999A

    公开(公告)日：1996-05-07

    申请号：US327723

    申请日：1994-10-24

    申请人： Vladimir Koifman ,  Yachin Afek

    发明人： Vladimir Koifman ,  Yachin Afek

    IPC分类号： H03M1/44 ,  H03F3/45 ,  H03H19/00 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H03M3/02 ,  H04L25/02 ,  H03F1/14

    CPC分类号： H04L25/0272 ,  H03F3/45479 ,  H03M1/0682 ,  H03M1/0863 ,  H04L25/0292 ,  H03F2200/331 ,  H03M1/12

    摘要： A differential switched capacitor circuit (6) for sampling a differential input signal (IP, IM) in different sampling phases (PHI0, PHI1) and for correcting errors at an output thereof, comprises:m switched capacitor stages (8-16) coupled in a chain, a first stage (8) being coupled to the output of the circuit, each of the m switched capacitor stages (8-16) being coupled to an adjacent stage in the chain depending on the sampling phase such that a charge representative of the error is equally shared between adjacent stages in the chain and wherein the mth stage (16) is selectively coupled to an end node so as to cancel the charge thereon, whereby after a number of sampling phases the error at the output is substantially reduced by a factor of up to 1/m.

    摘要翻译： 一种差分开关电容器电路（6），用于对不同采样相位（PHI0，PHI1）中的差分输入信号（IP，IM）进行采样，并用于在其输出端校正误差，包括：m个开关电容器级（8-16） 链路，第一级（8）耦合到电路的输出端，m个开关电容器级（8-16）中的每一个根据采样相位耦合到链中的相邻级，使得代表 误差在链中的相邻级之间同等地共享，并且其中第m级（16）选择性地耦合到端节点以消除其上的电荷，由此在多个采样相位之后，输出端的误差被大大地减小 高达1 / m的因子。