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1.发明授权Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit 失效在VLSI中央处理单元中二进制到二进制编码十进制和二进制编码十进制到二进制转换
公开(公告)号：US5251321A
公开(公告)日：1993-10-05
申请号：US954437
申请日：1992-09-30
申请人： Donald C. Boothroyd , Clinton B. Eckard , Ronald E. Lange , William A. Shelly , Ronald W. Yoder
发明人： Donald C. Boothroyd , Clinton B. Eckard , Ronald E. Lange , William A. Shelly , Ronald W. Yoder
CPC分类号： G06F9/30025 , H03M7/12
摘要： Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced. The resultant operand is sent to the conversion register. If the operand is negative, all bits are inverted, and a one is added to produce the resultant in two's complement notation.
摘要翻译： 二进制编码 - 十进制到二进制（DTB）和二进制到二进制编码十进制（BTD）指令由地址和执行（AX）芯片，十进制数字（DN）芯片和高速缓存执行。 对于DTB指令，DN芯片接收要从缓存转换的操作数，保存该符号，并将其存储在转换寄存器中。 当一个位被转换时，COMFROM总线上发送一个即时发送信号，COMTO总线上的就绪接收命令使AX芯片接受该位，并且DN芯片产生下一个位，直到 产生合成操作数。 如果要转换的操作数为负，则DN芯片在第一个“1”之后反转每个剩余的位，以获得二进制补码结果。 任一情况下的结果都将发送到缓存。 对于BTD指令，AX芯片接收要从高速缓存转换的操作数，将符号位发送到DN芯片，然后在即将发送和就绪准备就绪信号为零时，操作数的位 生产。 结果操作数被发送到转换寄存器。 如果操作数为负，则所有位都被反转，并且添加一个位以产生以二进制补码表示的结果。
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公开(公告)号：US5276862A
公开(公告)日：1994-01-04
申请号：US682801
申请日：1991-04-09
申请人： Lowell D. McCulley , Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards
发明人： Lowell D. McCulley , Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards
CPC分类号： G06F11/1441 , G06F11/1641 , G06F11/1637
摘要： In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.
摘要翻译： 为了收集，存储和交付（如果需要的话）中央处理器保险箱信息，采用多相时钟来捕获（一个完整的时钟周期）保存存储信息，这些信息通常包括所有（或选定的）数据操作中的所有软件可见寄存器 通过临时存储（在多相时钟的影响下）将缓存存储信息路由到高速缓存数据阵列中并进入特殊目的XRAM模块，从而使CPU的芯片。 因此，在检测到故障时，XRAM中有效的保险箱信息可用于分析，如果适用，在刚刚发生故障的连续点恢复运行。
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3.发明授权
公开(公告)号：US5263034A
公开(公告)日：1993-11-16
申请号：US594880
申请日：1990-10-09
申请人： Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards , Bruce E. Flocken
发明人： Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards , Bruce E. Flocken
IPC分类号： G06F11/16
CPC分类号： G06F11/1641
摘要： In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.
摘要翻译： 为了在包括AX（地址和执行）模块，DN（十进制数字）模块和FP（浮点））模块的中央处理器的基本处理单元（BPU）中提供有效的错误检测，每个模块在 主/从对，并且将每个对中执行的数据操作操作的本地结果进行比较，以便在结果被验证以供后续在中央处理器中使用之前进行身份验证。
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4.发明授权Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor count 失效中央处理器具有重复的基本处理单元，采用复用数据信号以减少单元间导体数
公开(公告)号：US5515529A
公开(公告)日：1996-05-07
申请号：US218538
申请日：1994-03-25
CPC分类号： G06F11/1633 , G06F11/10 , G06F12/0802
摘要： In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, a first BPU transfers to cache storage only the even bits of a given data manipulation result, and a second BPU correspondingly transfers to cache storage only the odd bit information of the result. One BPU segregates the even bits of the result, adds parity information and sends the even bits and parity information to the cache unit. Similarly, the second BPU segregates the odd bits of the result, adds parity information and sends the odd bits and parity information to the cache unit. In the cache unit, the even and odd bit information are separately parity checked before storage into cache memory. If a parity error is observed in either set of information, an error signal is issued to institute appropriate remedial action.
摘要翻译： 为了验证在一个CPU中的数据操作结果，该CPU结合了重复的BPU以完整性，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作操作，第一个BPU传输到缓存 仅存储给定数据操作结果的偶数位，并且第二BPU相应地将仅结果的奇数位信息传输到高速缓存存储器。 一个BPU分离结果的偶数位，添加奇偶校验信息，并将偶数位和奇偶校验信息发送到高速缓存单元。 类似地，第二BPU分离结果的奇数比特，添加奇偶校验信息，并将奇数比特和奇偶校验信息发送到高速缓存单元。 在高速缓存单元中，偶数和奇数比特信息在存储到高速缓冲存储器中之前被单独校验。 如果在任一组信息中观察到奇偶校验错误，则发出错误信号以进行适当的补救措施。
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5.发明授权Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count 失效具有重复的基本处理单元的中央处理器采用多路复用的高速缓存存储控制信号以减少单元间导体数
公开(公告)号：US5495579A
公开(公告)日：1996-02-27
申请号：US218532
申请日：1994-03-25
CPC分类号： G06F11/1654 , G06F11/10 , G06F11/1633
摘要： In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units or integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit for receiving data manipulation results from both BPUs and for transferring specified information words simultaneously to both BPUs upon request. These operations are controlled by cache interface control signals identically generated in each BPU. In each BPU, the control signals are arranged into first and second groups which are nominally identical. The first control signal group is transmitted to the cache unit from one BPU while the second control group is transmitted to the cache unit from the other BPU. In each BPU, parity is generated for each control group separately. Parity for the group sent to the cache unit by each BPU is included with the control signal information for checking in the cache unit. Parity for the group not sent to the cache unit by each BPU is transmitted to the other BPU and checked against the locally generated parity for that group. In the event of a parity miscompare sensed in either BPU or a parity error sensed in the cache unit, an error signal is issued to institute appropriate remedial action.
摘要翻译： 为了验证包含重复基本处理单元或完整性的CPU中的数据处理结果，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作以获得第一和第二数据 操作结果应该相同，以及用于从两个BPU接收数据操作结果并根据请求同时传送指定的信息字的缓存单元。 这些操作由在每个BPU中相同生成的高速缓存接口控制信号控制。 在每个BPU中，控制信号被布置成名义上相同的第一和第二组。 第一控制信号组从一个BPU发送到高速缓存单元，而第二控制组从另一个BPU发送到高速缓存单元。 在每个BPU中，分别为每个控制组生成奇偶校验。 用于由每个BPU发送到高速缓存单元的组的奇偶校验包括用于检查高速缓存单元的控制信号信息。 每个BPU未发送到高速缓存单元的组的奇偶校验被发送到另一个BPU，并针对该组的本地生成的奇偶校验进行检查。 在BPU中感测到的奇偶校验误差或在高速缓存单元中感测到的奇偶校验错误的情况下，发出错误信号以进行适当的补救动作。
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6.发明授权Basic operations synchronization and local mode controller in a VLSI central processor 失效VLSI中央处理器中的基本操作同步和本地模式控制器
公开(公告)号：US5644761A
公开(公告)日：1997-07-01
申请号：US893871
申请日：1992-06-05
申请人： Ronald W. Yoder , Ronald E. Lange , William A. Shelly , Russell W. Guenthner , Richard L. Demers
发明人： Ronald W. Yoder , Ronald E. Lange , William A. Shelly , Russell W. Guenthner , Richard L. Demers
CPC分类号： G06F9/267
摘要： In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.
摘要翻译： 为了有效地执行在中央处理单元中执行扩展指令所需的微步骤，提供了具有其自己的定序器的主序列控制器和单独的基本操作控制器以及半自主运行的能力。 通常，主序列控制器确定基本操作控制器的操作，但是在执行例如需要扩展基本操作的多字指令的情况下，基本操作控制器暂时控制主控制器，直到 扩展基本操作已经完成。 结果是相对简单的定序器，其支持紧密的微编码功能，其中许多顺序决定可以被预先确定。
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公开(公告)号：US6052700A
公开(公告)日：2000-04-18
申请号：US156104
申请日：1998-09-17
CPC分类号： G06F11/26 , G06F11/2242 , G06F11/24 , G06F1/14 , G06F12/0833
摘要： Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).
摘要翻译： 数据处理系统（80）中的每个处理器（92）缓存主日历时钟（97）的副本。 使用公共时钟（99）来周期性地增加主日历时钟（97）和所有缓存的日历时钟（272）。 只要系统（80）中的处理器（92）以新值加载主日历时钟（97），该处理器（92）向系统中的所有处理器广播高速缓存的日历时钟更新的中断信号（276）。 响应于该中断（278），每个处理器（92）清除其缓存的日历时钟有效标志（274）。 每当在处理器（92）上执行读取日历时钟指令时，测试标志（274），并且如果被设置，则返回其高速缓存的日历时钟（272）值。 否则，检索主日历时钟（97）值，写入该处理器的缓存日历时钟（272）并返回。 高速缓存的日历时钟有效标志（274）被设置为指示有效的高速缓存日历时钟（272）。
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8.发明授权公开(公告)号：US06223228B1
公开(公告)日：2001-04-24
申请号：US09156377
申请日：1998-09-17
IPC分类号： G06F112
CPC分类号： G06F9/30087 , G06F1/04 , G06F11/2236 , G06F11/3466
摘要： Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).
摘要翻译： 提供两个指令以同步数据处理系统（80）中的多个处理器（92）。 发送同步指令（TSYNC）向系统（80）中的所有活动处理器（92）发送同步处理器中断（276）。 处理器（92）通过执行等待同步（WSYNC）指令等待接收同步信号（278）。 等待这种信号（278）的每个处理器在接收到中断信号（278）之后的下一个时钟周期被激活。 提供可选的超时值以防止挂起错过中断的等待处理器（92）（278）。 每当通过接收到中断（278）激活WSYNC指令时，将启动跟踪以将固定数量的事件跟踪到内部跟踪缓存（58）。
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公开(公告)号：US06230263B1
公开(公告)日：2001-05-08
申请号：US09156376
申请日：1998-09-17
IPC分类号： G06F930
CPC分类号： G06F9/30079
摘要： A processor (92) in a data processing system (80) provides a DELAY instruction. Executing the DELAY instruction causes the processor (92) to a specified integral number of clock (98) cycles before continuing. Delays are guaranteed to have a linear relationship with a constant slope with the specified number of clock cycles. Incrementing the specified delay through a range allows exhaustive testing of interactions among multiple processors.
摘要翻译： 数据处理系统（80）中的处理器（92）提供DELAY指令。 执行DELAY指令使处理器（92）在指定的整数时钟（98）周期之前继续。 延迟保证与具有指定时钟周期数的恒定斜率具有线性关系。 通过一个范围增加指定的延迟允许对多个处理器之间的交互进行详尽的测试。
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10.发明授权Gate close failure notification for fair gating in a nonuniform memory architecture data processing system 有权门不合格故障通知，用于在不均匀的内存架构数据处理系统中进行公平门控公开(公告)号：US06480973B1
公开(公告)日：2002-11-12
申请号：US09409456
申请日：1999-09-30
IPC分类号： G06F1100
CPC分类号： G06F9/526
摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
摘要翻译： 在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。 对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。 在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决 试图关闭旋转门。 每个处理器检测何时在旋转门上旋转。 然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。
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