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    Programmable weak write test mode (PWWTM) bias generation having logic high output default mode
    3.
    发明授权
    Programmable weak write test mode (PWWTM) bias generation having logic high output default mode 失效
    具有逻辑高输出默认模式的可编程弱写入测试模式（PWWTM）偏置生成

    公开(公告)号：US07133319B2

    公开(公告)日：2006-11-07

    申请号：US10600878

    申请日：2003-06-20

    申请人： John Wuu ,  Blaine Stackhouse ,  Donald R. Weiss

    发明人： John Wuu ,  Blaine Stackhouse ,  Donald R. Weiss

    IPC分类号： G11C7/00

    CPC分类号： G11C29/028 ,  G11C11/41 ,  G11C29/12 ,  G11C29/12005

    摘要： The present invention employs a bias voltage having a selectable magnitude to bias a weak write pull-down transistor in a write driver of a static random access memory (SRAM) array. A programmable weak write test mode (PWWTM) bias generator includes an output signal that is a logic high in a default mode when a WWTM is not active. When the WWTM is active, the generator output signal is the bias voltage having the selectable magnitude. The default mode logic high is actively maintained when the generator output is connected to a load, such as the write driver of the SRAM array. A WWTM-enabled SRAM system includes the PWWTM bias generator. A method of driving a WWTM-equipped SRAM includes generating and applying the output signal to a gate of a weak write pull-down transistor of the SRAM array write driver in the default mode and the WWTM.

    摘要翻译： 本发明采用具有可选择量值的偏置电压来偏置静态随机存取存储器（SRAM）阵列的写入驱动器中的弱写入下拉晶体管。 可编程弱写入测试模式（PWWTM）偏置发生器包括当WWTM不活动时，默认模式下的逻辑高电平的输出信号。 当WWTM有效时，发生器输出信号是具有可选择量值的偏置电压。 当发电机输出连接到负载（如SRAM阵列的写入驱动器）时，主动保持默认模式逻辑高电平。 支持WWTM的SRAM系统包括PWWTM偏置发生器。 驱动配备有WWTM的SRAM的方法包括在默认模式和WWTM中产生并施加输出信号到SRAM阵列写入驱动器的弱写入下拉晶体管的栅极。

    Static random access memory (SRAM) array central global decoder system and method
    4.
    发明授权
    Static random access memory (SRAM) array central global decoder system and method 失效
    静态随机存取存储器（SRAM）阵列中央全局解码器系统及方法

    公开(公告)号：US06366526B2

    公开(公告)日：2002-04-02

    申请号：US09790132

    申请日：2001-02-21

    申请人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

    发明人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

    IPC分类号： G11C800

    CPC分类号： G11C8/10 ,  G11C11/418

    摘要： A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the memory cells for reading and writing operations. The SRAM cell is divided into groups of SRAM arrays of cells with a centrally located distributed global decoder to address any individual memory cell in the SRAM array. The global decoder accepts an addressing input and outputs a signal for selecting an individual column of memory cells in the SRAM array. The global decoder also outputs a signal selecting an individual row of memory cells contained in the SRAM array. The global decoder may include logic to decode addressing bits to produce a group select signal. Thus, the global decoder is able to select any single memory cell in the SRAM cell for reading or writing specific logical states.

    摘要翻译： 提供了一种静态随机存取存储器（SRAM）单元，其以可能的最大速度来优化存储器单元的阵列密度，以便对存储单元进行寻址和写入操作。 SRAM单元被分成具有位于中心的分布式全局解码器的SRAM阵列阵列，以解决SRAM阵列中的任何单独的存储单元。 全局解码器接受寻址输入并输出用于选择SRAM阵列中存储单元的单独列的信号。 全局解码器还输出选择SRAM阵列中包含的各行存储单元的信号。 全局解码器可以包括用于解码寻址位以产生组选择信号的逻辑。 因此，全局解码器能够选择SRAM单元中的任何单个存储器单元用于读取或写入特定的逻辑状态。

    Distributed decode system and method for improving static random access memory (SRAM) density
    5.
    发明授权
    Distributed decode system and method for improving static random access memory (SRAM) density 有权
    用于改进静态随机存取存储器（SRAM）密度的分布式解码系统和方法

    公开(公告)号：US06243287B1

    公开(公告)日：2001-06-05

    申请号：US09492510

    申请日：2000-01-27

    申请人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

    发明人： Samuel D Naffziger ,  Donald R Weiss ,  John Wuu

    IPC分类号： G11C1100

    CPC分类号： G11C8/10 ,  G11C11/418

    摘要： A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the memory cells for reading and writing operations. The SRAM cell is divided into groups of SRAM arrays of cells with a centrally located distributed global decoder to address any individual memory cell in the SRAM array. The global decoder includes a first logic block that accepts addressing input and outputs a signal for selecting an individual column of memory cells in the SRAM array. The global decoder includes a second logic block that accepts addressing input and outputs a signal selecting an individual row of memory cells contained in the SRAM array. The global decoder may include a third logic block to decode addressing bits to produce a group select signal. Thus, the global decoder is able to select any signal memory cell in the SRAM cell for reading or writing specific logical states.

    摘要翻译： 提供了一种静态随机存取存储器（SRAM）单元，其以阵列中的存储器单元的密度优化，以最大速度寻址存储器单元以进行读取和写入操作。 SRAM单元被分成具有位于中心的分布式全局解码器的SRAM阵列阵列，以解决SRAM阵列中的任何单独的存储单元。 全局解码器包括第一逻辑块，其接受寻址输入并输出用于选择SRAM阵列中的存储单元的单独列的信号。 全局解码器包括第二逻辑块，其接受寻址输入并输出选择SRAM阵列中包含的各行存储单元的信号。 全局解码器可以包括用于解码寻址位以产生组选择信号的第三逻辑块。 因此，全局解码器能够选择SRAM单元中的任何信号存储单元用于读取或写入特定的逻辑状态。

    Integrated weak write test mode (WWWTM)
    6.
    发明授权
    Integrated weak write test mode (WWWTM) 有权
    集成弱写测试模式（WWWTM）

    公开(公告)号：US06192001B1

    公开(公告)日：2001-02-20

    申请号：US09510287

    申请日：2000-02-21

    申请人： Donald R Weiss ,  John Wuu ,  Reid James Riedlinger

    发明人： Donald R Weiss ,  John Wuu ,  Reid James Riedlinger

    IPC分类号： G11C810

    CPC分类号： G11C11/419

    摘要： The present invention integrates a WWTM circuit with the write driver circuitry, which is an inherent part of any conventional SRAM design. Thus, a circuit for writing data into and weak write testing a memory cell is provided. In one embodiment, the circuit comprises a write driver that has an output for applying a write or a weak write output signal at the memory cell. The write driver has first and second selectable operating modes. In the first mode, the write driver is set to apply a weak write output signal from the output for performing a weak write test on the cell. In the second mode, the write driver is set to apply a normal write output signal that is sufficiently strong for writing a data value into the cell when it is healthy.

    摘要翻译： 本发明将WWTM电路与写驱动器电路集成，该驱动器电路是任何常规SRAM设计的固有部分。 因此，提供了用于将数据写入并弱写入测试存储器单元的电路。 在一个实施例中，电路包括具有用于在存储器单元处施加写入或弱写入输出信号的输出的写入驱动器。 写驱动器具有第一和第二可选操作模式。 在第一模式中，写入驱动器被设置为从输出端施加弱写入输出信号，以对单元执行弱写入测试。 在第二模式中，写入驱动器被设置为施加足够强的正常写入输出信号，以便当数据值健康时将数据值写入单元。

    Memory device and method of refreshing
    7.
    发明授权
    Memory device and method of refreshing 有权
    内存设备和刷新方法

    公开(公告)号：US07724567B2

    公开(公告)日：2010-05-25

    申请号：US12167821

    申请日：2008-07-03

    申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

    发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

    IPC分类号： G11C11/36

    CPC分类号： G11C15/04 ,  G06F12/0864 ,  G06F12/0895 ,  G11C11/39

    摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

    摘要翻译： 内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。 第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平 匹配检测操作。 内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

    MEMORY DEVICE AND METHOD
    8.
    发明申请
    MEMORY DEVICE AND METHOD 审中-公开
    存储器件和方法

    公开(公告)号：US20100002482A1

    公开(公告)日：2010-01-07

    申请号：US12167823

    申请日：2008-07-03

    申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

    发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C11/39

    摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

    摘要翻译： 内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。 第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平 匹配检测操作。 内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

    Circuit supply voltage control using an error sensor
    9.
    发明申请
    Circuit supply voltage control using an error sensor 审中-公开
    使用误差传感器的电路电源电压控制

    公开(公告)号：US20070229147A1

    公开(公告)日：2007-10-04

    申请号：US11395475

    申请日：2006-03-30

    申请人： Bruce Doyle ,  Manish Kumar ,  John Wuu ,  Samuel Naffziger

    发明人： Bruce Doyle ,  Manish Kumar ,  John Wuu ,  Samuel Naffziger

    IPC分类号： G05F1/10

    CPC分类号： G05F1/46

    摘要： For one disclosed embodiment, a supply voltage regulator is to control voltage at a first supply node for a circuit. The supply voltage regulator includes one or more first devices to couple the first supply node to a second supply node when the circuit is in a predetermined operational state and includes an error sensor to control the one or more first devices. The supply voltage regulator includes one or more second devices to couple the first supply node to a third supply node when the circuit is in the predetermined operational state. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，电源电压调节器用于控制电路的第一供电节点处的电压。 电源电压调节器包括一个或多个第一器件，用于当电路处于预定操作状态时将第一电源节点耦合到第二电源节点，并且包括用于控制一个或多个第一器件的误差传感器。 电源稳压器包括一个或多个第二设备，用于当电路处于预定操作状态时将第一供电节点耦合到第三供电节点。 还公开了其他实施例。

    SYSTEM AND METHOD FOR CALIBRATING WEAK WRITE TEST MODE (WWTM)
    10.
    发明申请
    SYSTEM AND METHOD FOR CALIBRATING WEAK WRITE TEST MODE (WWTM) 失效
    用于校准弱写入测试模式的系统和方法（WWTM）

    公开(公告)号：US20060142962A1

    公开(公告)日：2006-06-29

    申请号：US11024086

    申请日：2004-12-28

    申请人： Donald Weiss ,  Richard Woodruff ,  John Wuu

    发明人： Donald Weiss ,  Richard Woodruff ,  John Wuu

    IPC分类号： G01R19/00

    CPC分类号： G11C29/028 ,  G11C11/41 ,  G11C11/419 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/5006

    摘要： According to at least one embodiment, a method comprises measuring drive current of a reference memory cell of a circuit, and determining, based on the measured drive current of the reference memory cell, a drive current to be supplied to a calibration memory cell of the circuit to mimic a defective memory cell. The method further comprises supplying the determined drive current to the calibration memory cell, and using the calibration memory cell to determine strength of a weak write to be utilized by a weak write test for detecting defective memory cells.

    摘要翻译： 根据至少一个实施例，一种方法包括测量电路的参考存储单元的驱动电流，以及基于所测量的参考存储单元的驱动电流来确定要提供给该参考存储单元的校准存储单元的驱动电流 电路以模拟有缺陷的存储器单元。 该方法还包括将确定的驱动电流提供给校准存储单元，以及使用校准存储单元来确定弱写入测试用于检测有缺陷的存储器单元的弱写入的强度。